diff mbox

[4/5] lib/igt_draw: Add Y-tiling support for IGT_DRAW_BLT method

Message ID 1484550948-8649-4-git-send-email-praveen.paneri@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Praveen Paneri Jan. 16, 2017, 7:15 a.m. UTC 
From: Akash Goel <akash.goel@intel.com>

Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 lib/igt_draw.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
diff mbox

Patch

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 0b04a59..e8fae1a 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -31,6 +31,7 @@ 
 #include "igt_core.h"
 #include "igt_fb.h"
 #include "ioctl_wrappers.h"
+#include "i830_reg.h"
 
 /**
  * SECTION:igt_draw
@@ -487,6 +488,26 @@  static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 	blt_cmd_tiling = (tiling) ? XY_COLOR_BLT_TILED : 0;
 	pitch = (tiling) ? buf->stride / 4 : buf->stride;
 
+	if (tiling == I915_TILING_Y) {
+		/*
+		 * To change the tile register, insert an MI_FLUSH_DW
+		 * followed by an MI_LOAD_REGISTER_IMM
+		 */
+		BEGIN_BATCH(4, 0);
+		OUT_BATCH(MI_FLUSH_DW | 2);
+		OUT_BATCH(0x0);
+		OUT_BATCH(0x0);
+		OUT_BATCH(0x0);
+		ADVANCE_BATCH();
+
+		BEGIN_BATCH(4, 0);
+		OUT_BATCH(MI_LOAD_REGISTER_IMM);
+		OUT_BATCH(0x22200); /* BCS_SWCTRL */
+		OUT_BATCH(((0x3 << 16) | 0x3)); /* enable the Y tiling */
+		OUT_BATCH(MI_NOOP);
+		ADVANCE_BATCH();
+	}
+
 	BEGIN_BATCH(6, 1);
 	OUT_BATCH(XY_COLOR_BLT_CMD_NOLEN | XY_COLOR_BLT_WRITE_ALPHA |
 		  XY_COLOR_BLT_WRITE_RGB | blt_cmd_tiling | blt_cmd_len);
@@ -497,6 +518,26 @@  static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 	OUT_BATCH(color);
 	ADVANCE_BATCH();
 
+	if (tiling == I915_TILING_Y) {
+		/*
+		 * To change the tile register, insert an MI_FLUSH_DW
+		 * followed by an MI_LOAD_REGISTER_IMM
+		 */
+		BEGIN_BATCH(4, 0);
+		OUT_BATCH(MI_FLUSH_DW | 2);
+		OUT_BATCH(0x0);
+		OUT_BATCH(0x0);
+		OUT_BATCH(0x0);
+		ADVANCE_BATCH();
+
+		BEGIN_BATCH(4, 0);
+		OUT_BATCH(MI_LOAD_REGISTER_IMM);
+		OUT_BATCH(0x22200); /* BCS_SWCTRL */
+		OUT_BATCH((0x3 << 16)); /* Reset back to X-Tiling (default) */
+		OUT_BATCH(MI_NOOP);
+		ADVANCE_BATCH();
+	}
+
 	intel_batchbuffer_flush(batch);
 	intel_batchbuffer_free(batch);
 }