diff mbox

[7/7] drm/i915: Upclock on the first residency calculation

Message ID 1489497449-31640-7-git-send-email-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala March 14, 2017, 1:17 p.m. UTC
After ei reset, upclock as default if we don't have a previous
timestamp at hand. We might at sometimes waste one interval
of more power but also be more agile if we need to ramp up.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Chris Wilson March 14, 2017, 1:34 p.m. UTC | #1
On Tue, Mar 14, 2017 at 03:17:29PM +0200, Mika Kuoppala wrote:
> After ei reset, upclock as default if we don't have a previous
> timestamp at hand. We might at sometimes waste one interval
> of more power but also be more agile if we need to ramp up.

Why? There is nothing special about the first EI interval - it doesn't
correspond to GPU activity. We already start from rpe which is about 75%
of max on that platform. At the first sign that we are underperforming
we will overcompensate.
-Chris
Mika Kuoppala March 14, 2017, 1:36 p.m. UTC | #2
Chris Wilson <chris@chris-wilson.co.uk> writes:

> On Tue, Mar 14, 2017 at 03:17:29PM +0200, Mika Kuoppala wrote:
>> After ei reset, upclock as default if we don't have a previous
>> timestamp at hand. We might at sometimes waste one interval
>> of more power but also be more agile if we need to ramp up.
>
> Why? There is nothing special about the first EI interval - it doesn't
> correspond to GPU activity. We already start from rpe which is about 75%
> of max on that platform. At the first sign that we are underperforming
> we will overcompensate.

Then I have misunderstood the rampup and need to reread it. This patch
can be ignored.

-Mika

> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5ec12cf..aacb654 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1118,6 +1118,8 @@  static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 			events = GEN6_PM_RP_UP_THRESHOLD;
 		else if (c0 < time * dev_priv->rps.down_threshold)
 			events = GEN6_PM_RP_DOWN_THRESHOLD;
+	} else {
+		events = GEN6_PM_RP_UP_THRESHOLD;
 	}
 
 	dev_priv->rps.ei = now;