From patchwork Wed Mar 15 06:59:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Paneri X-Patchwork-Id: 9624945 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8DB8F604CC for ; Wed, 15 Mar 2017 06:52:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DB88285F3 for ; Wed, 15 Mar 2017 06:52:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 709C0285F5; Wed, 15 Mar 2017 06:52:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DDAE5285F3 for ; Wed, 15 Mar 2017 06:52:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0DF896E7E6; Wed, 15 Mar 2017 06:52:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AEE2A6E7E6 for ; Wed, 15 Mar 2017 06:52:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489560749; x=1521096749; h=from:to:cc:subject:date:message-id; bh=2FOk2c0p60+MRQP/zZ8P6bVfJ35UxH08Fv4YZYUsXgo=; b=NKVoWSq6YbcOcPvipo1+UdOfns0jVgKht6GL+WtY/UJdR4BMhLzfWzL7 6hSG/pNqAEylIgWn4Wdjp4lmBoM8zw==; Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2017 23:52:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,167,1486454400"; d="scan'208";a="67538895" Received: from intel-desktop.iind.intel.com ([10.223.82.55]) by orsmga004.jf.intel.com with ESMTP; 14 Mar 2017 23:52:27 -0700 From: Praveen Paneri To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Mar 2017 12:29:35 +0530 Message-Id: <1489561175-27470-1-git-send-email-praveen.paneri@intel.com> X-Mailer: git-send-email 1.9.1 Cc: paulo.r.zanoni@intel.com, Praveen Paneri Subject: [Intel-gfx] [PATCH] drm/i915: Enable FBC for non X-tiled FBs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP FBC is only enabled for X-tiled framebuffers but there are quite a few cases where we tend to use Y-tiled framebuffers. So enabling it for non X-tiled framebuffers. Signed-off-by: Praveen Paneri --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc843f9..9d7a376 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2506,6 +2506,8 @@ enum skl_disp_power_wells { #define BDW_FBC_COMPRESSION_MASK 0xfff #define FBC_LL_SIZE (1536) +#define FBC_YSTRIDE _MMIO(0x4208c) +#define FBC_STRIDE_OVERRIDE (1<<13) #define FBC_LLC_READ_CTRL _MMIO(0x9044) #define FBC_LLC_FULLY_OPEN (1<<30) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 17d418b..0ac9889 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -301,6 +301,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; + if (INTEL_GEN(dev_priv) >= 9 && + i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) { + struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache; + int cfb_stride = DIV_ROUND_UP(cache->plane.src_w, + (32 * threshold)) * 8; + I915_WRITE(FBC_YSTRIDE, FBC_STRIDE_OVERRIDE | cfb_stride); + } + dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);