From patchwork Wed Mar 15 15:43:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 9625965 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3A53D604A9 for ; Wed, 15 Mar 2017 15:43:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DD5728642 for ; Wed, 15 Mar 2017 15:43:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 22E222864B; Wed, 15 Mar 2017 15:43:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6B0472864A for ; Wed, 15 Mar 2017 15:43:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA5916E910; Wed, 15 Mar 2017 15:43:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id E66866E910 for ; Wed, 15 Mar 2017 15:43:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489592627; x=1521128627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J08rnKsTuxrorC7yPmyGJwPXQNSKSx+4oC2DDhPKM/g=; b=LsopDScdbEbCaRMnzgaRraA4ghHWsI3P0+zMhU4M1pDcTPIdaBprI5+S Z99QZGaSI0QdEzFNN2ihg6HKnpx/lQ==; Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2017 08:43:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,169,1486454400"; d="scan'208"; a="1142636649" Received: from rosetta.fi.intel.com ([10.237.72.176]) by fmsmga002.fm.intel.com with ESMTP; 15 Mar 2017 08:43:45 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 6D24784262B; Wed, 15 Mar 2017 17:43:06 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Mar 2017 17:43:01 +0200 Message-Id: <1489592584-10422-3-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489592584-10422-1-git-send-email-mika.kuoppala@intel.com> References: <1489592584-10422-1-git-send-email-mika.kuoppala@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Extend vlv/chv residency resolution X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Vlv and chv residency counters are 40 bits in width. With a control bit, we can choose between upper or lower 32 bit window into this counter. Lets toggle this bit on and off on and read both parts. As a result we can push the wrap from 13 seconds to 54 minutes. v2: commit msg, loop readability, goto elimination (Chris) Reported-by: Len Brown Cc: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 60 +++++++++++++++++++++++++++++++++++------ 1 file changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index da742a9..19fd11b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8350,12 +8350,51 @@ void intel_pm_setup(struct drm_i915_private *dev_priv) atomic_set(&dev_priv->pm.wakeref_count, 0); } +static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, + const i915_reg_t reg) +{ + u32 lower, upper, tmp, saved_ctl; + + /* The register accessed do not need forcewake. We borrow + * uncore lock to prevent concurrent access to range reg. + */ + spin_lock_irq(&dev_priv->uncore.lock); + saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL); + + if (!(saved_ctl & VLV_COUNT_RANGE_HIGH)) + I915_WRITE_FW(VLV_COUNTER_CONTROL, + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); + + /* vlv and chv residency counters are 40 bits in width. + * With a control bit, we can choose between upper or lower + * 32bit window into this counter. + */ + upper = I915_READ_FW(reg); + do { + tmp = upper; + + I915_WRITE_FW(VLV_COUNTER_CONTROL, + _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); + lower = I915_READ_FW(reg); + + I915_WRITE_FW(VLV_COUNTER_CONTROL, + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); + upper = I915_READ_FW(reg); + } while (upper != tmp); + + if (!(saved_ctl & VLV_COUNT_RANGE_HIGH)) + I915_WRITE_FW(VLV_COUNTER_CONTROL, + _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); + + spin_unlock_irq(&dev_priv->uncore.lock); + + return lower | (u64)upper << 8; +} + u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, const i915_reg_t reg) { - u64 raw_time; /* 32b value may overflow during fixed point math */ - u64 units = 128000ULL, div = 100000ULL; - u64 ret; + u64 time_hw, units, div, residency_us; if (!intel_enable_rc6()) return 0; @@ -8367,16 +8406,21 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, units = 1000; div = dev_priv->czclk_freq; - if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) - units <<= 8; + time_hw = vlv_residency_raw(dev_priv, reg); } else if (IS_GEN9_LP(dev_priv)) { units = 1000; div = 1200; /* 833.33ns */ + + time_hw = I915_READ(reg); + } else { + units = 128000; /* 1.28us */ + div = 100000; + + time_hw = I915_READ(reg); } - raw_time = I915_READ(reg) * units; - ret = DIV_ROUND_UP_ULL(raw_time, div); + residency_us = DIV_ROUND_UP_ULL(time_hw * units, div); intel_runtime_pm_put(dev_priv); - return ret; + return residency_us; }