From patchwork Wed Mar 15 15:43:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 9625963 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0C29A604A9 for ; Wed, 15 Mar 2017 15:43:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3D6D28642 for ; Wed, 15 Mar 2017 15:43:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E87BB2864F; Wed, 15 Mar 2017 15:43:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0186128642 for ; Wed, 15 Mar 2017 15:43:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A35596E906; Wed, 15 Mar 2017 15:43:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8790D6E906 for ; Wed, 15 Mar 2017 15:43:48 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 15 Mar 2017 08:43:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,169,1486454400"; d="scan'208";a="834968356" Received: from rosetta.fi.intel.com ([10.237.72.176]) by FMSMGA003.fm.intel.com with ESMTP; 15 Mar 2017 08:43:46 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 72BD884262E; Wed, 15 Mar 2017 17:43:06 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Mar 2017 17:43:04 +0200 Message-Id: <1489592584-10422-6-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489592584-10422-1-git-send-email-mika.kuoppala@intel.com> References: <1489592584-10422-1-git-send-email-mika.kuoppala@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Use coarse grained residency counter with byt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Set byt rc residency counters high level as chv does by default. We lose some accuracy on byt but we can do the calculation without extra hw read on both platforms, as now they behave identically in this respect. v2: use ktime Cc: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_irq.c | 9 ++------- drivers/gpu/drm/i915/intel_pm.c | 9 +++------ 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f73d8db..7fb35a5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1100,11 +1100,6 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) if (prev->ktime) { u64 time, c0; u32 render, media; - unsigned int mul; - - mul = 1000 * 100; /* scale to threshold% */ - if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) - mul <<= 8; time = ktime_us_delta(now.ktime, prev->ktime); time *= dev_priv->czclk_freq; @@ -1116,8 +1111,8 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) */ render = now.render_c0 - prev->render_c0; media = now.media_c0 - prev->media_c0; - c0 = max(render, media); - c0 *= mul; + c0 = max_t(u64, render, media) << 8; /* upper part of 40 bit */ + c0 *= 1000 * 100; /* to usecs and scale to threshold% */ if (c0 > time * dev_priv->rps.up_threshold) events = GEN6_PM_RP_UP_THRESHOLD; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 19fd11b..41d85ce 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6392,7 +6392,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) /* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, - _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | + VLV_MEDIA_RC0_COUNT_EN | VLV_RENDER_RC0_COUNT_EN | VLV_MEDIA_RC6_COUNT_EN | VLV_RENDER_RC6_COUNT_EN)); @@ -8361,7 +8362,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, spin_lock_irq(&dev_priv->uncore.lock); saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL); - if (!(saved_ctl & VLV_COUNT_RANGE_HIGH)) + if (WARN_ON(!(saved_ctl & VLV_COUNT_RANGE_HIGH))) I915_WRITE_FW(VLV_COUNTER_CONTROL, _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); @@ -8382,10 +8383,6 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, upper = I915_READ_FW(reg); } while (upper != tmp); - if (!(saved_ctl & VLV_COUNT_RANGE_HIGH)) - I915_WRITE_FW(VLV_COUNTER_CONTROL, - _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); - spin_unlock_irq(&dev_priv->uncore.lock); return lower | (u64)upper << 8;