From patchwork Thu Mar 16 16:32:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9628931 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4B00F604AA for ; Thu, 16 Mar 2017 16:30:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C7E5285EE for ; Thu, 16 Mar 2017 16:30:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3169C2860C; Thu, 16 Mar 2017 16:30:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95BB228604 for ; Thu, 16 Mar 2017 16:30:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 413F96EB4A; Thu, 16 Mar 2017 16:30:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9EDF56EB72 for ; Thu, 16 Mar 2017 16:30:20 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 09:30:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,173,1486454400"; d="scan'208";a="68094227" Received: from sakamble-desktop.iind.intel.com ([10.223.82.153]) by orsmga004.jf.intel.com with ESMTP; 16 Mar 2017 09:30:19 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Mar 2017 22:02:16 +0530 Message-Id: <1489681945-14058-15-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489681945-14058-1-git-send-email-sagar.a.kamble@intel.com> References: <1489681945-14058-1-git-send-email-sagar.a.kamble@intel.com> Cc: Tom O'Rourke Subject: [Intel-gfx] [PATCH v6 14/23] drm/i915/slpc: Add parameter set/unset/get functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP SLPC behavior can be changed through set of parameters. These parameters can be updated and queried from i915 though Host to GuC SLPC events. This patch add parameter values and events for setting/unsetting parameters. v1: Use host2guc_slpc update slcp_param_id enum values for SLPC 2015.2.4 return void instead of ignored error code (Paulo) v2: Checkpatch update. v3: Rebase. v4: Updated with GuC firmware v9. v5: Updated input structure to host2guc_slpc. Added functions to update only parameters in the SLPC shared memory. This will allow to setup shared data with all parameters and send single event to SLPC take them into effect. Commit message update. (Sagar) v6: Rearranged helpers to use them in slpc_shared_data_init. Added definition of SLPC_KMD_MAX_PARAM. Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_slpc.c | 104 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 29 +++++++++++ 2 files changed, 133 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 10d9af2..5497e07 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -52,6 +52,23 @@ static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv) return slice_count; } +void slpc_mem_set_param(struct slpc_shared_data *data, + u32 id, + u32 value) +{ + data->override_parameters_set_bits[id >> 5] + |= (1 << (id % 32)); + data->override_parameters_values[id] = value; +} + +void slpc_mem_unset_param(struct slpc_shared_data *data, + u32 id) +{ + data->override_parameters_set_bits[id >> 5] + &= (~(1 << (id % 32))); + data->override_parameters_values[id] = 0; +} + static void slpc_shared_data_init(struct drm_i915_private *dev_priv) { struct page *page; @@ -144,6 +161,29 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv) host2guc_slpc(dev_priv, &data, 4); } +static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv, + u32 id, u32 value) +{ + struct slpc_event_input data = {0}; + + data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2); + data.args[0] = id; + data.args[1] = value; + + host2guc_slpc(dev_priv, &data, 4); +} + +static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv, + u32 id) +{ + struct slpc_event_input data = {0}; + + data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1); + data.args[0] = id; + + host2guc_slpc(dev_priv, &data, 3); +} + void intel_slpc_query_task_state(struct drm_i915_private *dev_priv) { if (dev_priv->guc.slpc.active) @@ -221,6 +261,70 @@ bool intel_slpc_get_status(struct drm_i915_private *dev_priv) return ret; } +void intel_slpc_set_param(struct drm_i915_private *dev_priv, + u32 id, + u32 value) +{ + struct page *page; + struct slpc_shared_data *data = NULL; + + WARN_ON(id >= SLPC_MAX_PARAM); + + if (!dev_priv->guc.slpc.vma) + return; + + page = i915_vma_first_page(dev_priv->guc.slpc.vma); + data = kmap_atomic(page); + slpc_mem_set_param(data, id, value); + kunmap_atomic(data); + + host2guc_slpc_set_param(dev_priv, id, value); +} + +void intel_slpc_unset_param(struct drm_i915_private *dev_priv, + u32 id) +{ + struct page *page; + struct slpc_shared_data *data = NULL; + + WARN_ON(id >= SLPC_MAX_PARAM); + + if (!dev_priv->guc.slpc.vma) + return; + + page = i915_vma_first_page(dev_priv->guc.slpc.vma); + data = kmap_atomic(page); + slpc_mem_unset_param(data, id); + kunmap_atomic(data); + + host2guc_slpc_unset_param(dev_priv, id); +} + +void intel_slpc_get_param(struct drm_i915_private *dev_priv, + u32 id, + int *overriding, u32 *value) +{ + struct page *page; + struct slpc_shared_data *data = NULL; + u32 bits; + + WARN_ON(id >= SLPC_MAX_PARAM); + + if (!dev_priv->guc.slpc.vma) + return; + + page = i915_vma_first_page(dev_priv->guc.slpc.vma); + data = kmap_atomic(page); + if (overriding) { + bits = data->override_parameters_set_bits[id >> 5]; + *overriding = (0 != (bits & (1 << (id % 32)))); + } + if (value) + *value = data->override_parameters_values[id]; + + kunmap_atomic(data); +} + void intel_slpc_init(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index 567b9a3..360f3f2 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -194,11 +194,40 @@ enum slpc_status { SLPC_STATUS_NO_LOCK = 22, }; +enum slpc_param_id { + SLPC_PARAM_TASK_ENABLE_GTPERF = 0, + SLPC_PARAM_TASK_DISABLE_GTPERF = 1, + SLPC_PARAM_TASK_ENABLE_BALANCER = 2, + SLPC_PARAM_TASK_DISABLE_BALANCER = 3, + SLPC_PARAM_TASK_ENABLE_DCC = 4, + SLPC_PARAM_TASK_DISABLE_DCC = 5, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6, + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7, + SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8, + SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9, + SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10, + SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11, + SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12, + SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13, + SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14, + SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15, + SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16, + SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17, + SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18, + SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19, + SLPC_MAX_PARAM, + SLPC_KMD_MAX_PARAM = 32, +}; + /* intel_slpc.c */ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv, struct slpc_shared_data *data); const char *intel_slpc_get_state_str(enum slpc_global_state state); bool intel_slpc_get_status(struct drm_i915_private *dev_priv); +void intel_slpc_set_param(struct drm_i915_private *dev_priv, u32 id, u32 value); +void intel_slpc_unset_param(struct drm_i915_private *dev_priv, u32 id); +void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id, + int *overriding, u32 *value); void intel_slpc_init(struct drm_i915_private *dev_priv); void intel_slpc_cleanup(struct drm_i915_private *dev_priv); void intel_slpc_enable(struct drm_i915_private *dev_priv);