From patchwork Thu Mar 16 16:32:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9628937 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A9B9E604AA for ; Thu, 16 Mar 2017 16:30:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A819285EE for ; Thu, 16 Mar 2017 16:30:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F5AA2860C; Thu, 16 Mar 2017 16:30:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E47C6285EE for ; Thu, 16 Mar 2017 16:30:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AD196EB82; Thu, 16 Mar 2017 16:30:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id D39C06EB82 for ; Thu, 16 Mar 2017 16:30:24 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 09:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,173,1486454400"; d="scan'208";a="68094256" Received: from sakamble-desktop.iind.intel.com ([10.223.82.153]) by orsmga004.jf.intel.com with ESMTP; 16 Mar 2017 09:30:23 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Mar 2017 22:02:19 +0530 Message-Id: <1489681945-14058-18-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489681945-14058-1-git-send-email-sagar.a.kamble@intel.com> References: <1489681945-14058-1-git-send-email-sagar.a.kamble@intel.com> Cc: Tom O'Rourke Subject: [Intel-gfx] [PATCH v6 17/23] drm/i915/slpc: Add enable/disable controls for SLPC tasks X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke Adds debugfs hooks for enabling/disabling each SLPC task. The enable/disable debugfs files are i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc. Each of these can take the values: "default", "enabled", or "disabled" v1: update for SLPC v2015.2.4 dfps and turbo merged and renamed "gtperf" ibc split out and renamed "balancer" Avoid magic numbers (Jon Bloomfield) v2-v3: Rebase. v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared separate functions to update the task status only in the SLPC shared memory. Passing dev_priv as parameter. v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write. Moved functions to intel_slpc.c. RPM Get/Put added before setting parameters and sending RESET event explicitly. (Sagar) Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 3 + drivers/gpu/drm/i915/intel_slpc.c | 277 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 12 ++ 3 files changed, 292 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 579a8b2..3ea802c4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4858,6 +4858,9 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) const struct file_operations *fops; } i915_debugfs_files[] = { {"i915_wedged", &i915_wedged_fops}, + {"i915_slpc_gtperf", &i915_slpc_gtperf_fops}, + {"i915_slpc_balancer", &i915_slpc_balancer_fops}, + {"i915_slpc_dcc", &i915_slpc_dcc_fops}, {"i915_max_freq", &i915_max_freq_fops}, {"i915_min_freq", &i915_min_freq_fops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 8e351f7..e944da2 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -225,6 +225,189 @@ static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf, .write = slpc_param_ctl_write }; +static void slpc_task_param_show(struct seq_file *m, u32 enable_id, + u32 disable_id) +{ + struct drm_i915_private *dev_priv = m->private; + const char *status; + u64 val; + int ret; + + ret = intel_slpc_task_status(dev_priv, &val, enable_id, disable_id); + + if (ret) { + seq_printf(m, "error %d\n", ret); + } else { + switch (val) { + case SLPC_PARAM_TASK_DEFAULT: + status = "default\n"; + break; + + case SLPC_PARAM_TASK_ENABLED: + status = "enabled\n"; + break; + + case SLPC_PARAM_TASK_DISABLED: + status = "disabled\n"; + break; + + default: + status = "unknown\n"; + break; + } + + seq_puts(m, status); + } +} + +static int slpc_task_param_write(struct seq_file *m, const char __user *ubuf, + size_t len, u32 enable_id, u32 disable_id) +{ + struct drm_i915_private *dev_priv = m->private; + u64 val; + int ret = 0; + char buf[10]; + + if (len >= sizeof(buf)) + ret = -EINVAL; + else if (copy_from_user(buf, ubuf, len)) + ret = -EFAULT; + else + buf[len] = '\0'; + + if (!ret) { + if (!strncmp(buf, "default", 7)) + val = SLPC_PARAM_TASK_DEFAULT; + else if (!strncmp(buf, "enabled", 7)) + val = SLPC_PARAM_TASK_ENABLED; + else if (!strncmp(buf, "disabled", 8)) + val = SLPC_PARAM_TASK_DISABLED; + else + ret = -EINVAL; + } + + if (!ret) + ret = intel_slpc_task_control(dev_priv, val, enable_id, + disable_id); + + return ret; +} + +static int slpc_gtperf_show(struct seq_file *m, void *data) +{ + slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF, + SLPC_PARAM_TASK_DISABLE_GTPERF); + + return 0; +} + +static int slpc_gtperf_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + return single_open(file, slpc_gtperf_show, dev_priv); +} + +static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + int ret = 0; + + ret = slpc_task_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF, + SLPC_PARAM_TASK_DISABLE_GTPERF); + if (ret) + return ret; + + return len; +} + +const struct file_operations i915_slpc_gtperf_fops = { + .owner = THIS_MODULE, + .open = slpc_gtperf_open, + .release = single_release, + .read = seq_read, + .write = slpc_gtperf_write, + .llseek = seq_lseek +}; + +static int slpc_balancer_show(struct seq_file *m, void *data) +{ + slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER, + SLPC_PARAM_TASK_DISABLE_BALANCER); + + return 0; +} + +static int slpc_balancer_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + return single_open(file, slpc_balancer_show, dev_priv); +} + +static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + int ret = 0; + + ret = slpc_task_param_write(m, ubuf, len, + SLPC_PARAM_TASK_ENABLE_BALANCER, + SLPC_PARAM_TASK_DISABLE_BALANCER); + if (ret) + return ret; + + return len; +} + +const struct file_operations i915_slpc_balancer_fops = { + .owner = THIS_MODULE, + .open = slpc_balancer_open, + .release = single_release, + .read = seq_read, + .write = slpc_balancer_write, + .llseek = seq_lseek +}; + +static int slpc_dcc_show(struct seq_file *m, void *data) +{ + slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC, + SLPC_PARAM_TASK_DISABLE_DCC); + + return 0; +} + +static int slpc_dcc_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + return single_open(file, slpc_dcc_show, dev_priv); +} + +static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + int ret = 0; + + ret = slpc_task_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC, + SLPC_PARAM_TASK_DISABLE_DCC); + if (ret) + return ret; + + return len; +} + +const struct file_operations i915_slpc_dcc_fops = { + .owner = THIS_MODULE, + .open = slpc_dcc_open, + .release = single_release, + .read = seq_read, + .write = slpc_dcc_write, + .llseek = seq_lseek +}; + static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv) { enum slpc_platform_sku platform_sku; @@ -268,6 +451,30 @@ void slpc_mem_unset_param(struct slpc_shared_data *data, data->override_parameters_values[id] = 0; } +int slpc_mem_task_control(struct slpc_shared_data *data, u64 val, + u32 enable_id, u32 disable_id) +{ + int ret = 0; + + if (val == SLPC_PARAM_TASK_DEFAULT) { + /* set default */ + slpc_mem_unset_param(data, enable_id); + slpc_mem_unset_param(data, disable_id); + } else if (val == SLPC_PARAM_TASK_ENABLED) { + /* set enable */ + slpc_mem_set_param(data, enable_id, 1); + slpc_mem_unset_param(data, disable_id); + } else if (val == SLPC_PARAM_TASK_DISABLED) { + /* set disable */ + slpc_mem_set_param(data, disable_id, 1); + slpc_mem_unset_param(data, enable_id); + } else { + ret = -EINVAL; + } + + return ret; +} + static void slpc_shared_data_init(struct drm_i915_private *dev_priv) { struct page *page; @@ -579,6 +786,76 @@ int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val) return 0; } +int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val, + u32 enable_id, u32 disable_id) +{ + int ret = 0; + + if (!dev_priv->guc.slpc.active) + return -ENODEV; + + intel_runtime_pm_get(dev_priv); + + if (val == SLPC_PARAM_TASK_DEFAULT) { + /* set default */ + intel_slpc_unset_param(dev_priv, enable_id); + intel_slpc_unset_param(dev_priv, disable_id); + } else if (val == SLPC_PARAM_TASK_ENABLED) { + /* set enable */ + intel_slpc_set_param(dev_priv, enable_id, 1); + intel_slpc_unset_param(dev_priv, disable_id); + } else if (val == SLPC_PARAM_TASK_DISABLED) { + /* set disable */ + intel_slpc_set_param(dev_priv, disable_id, 1); + intel_slpc_unset_param(dev_priv, enable_id); + } else { + ret = -EINVAL; + } + + intel_slpc_enable(dev_priv); + intel_runtime_pm_put(dev_priv); + + return ret; +} + +int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val, + u32 enable_id, u32 disable_id) +{ + int override_enable, override_disable; + u32 value_enable, value_disable; + int ret = 0; + + if (!dev_priv->guc.slpc.active) { + ret = -ENODEV; + } else if (val) { + intel_slpc_get_param(dev_priv, enable_id, &override_enable, + &value_enable); + intel_slpc_get_param(dev_priv, disable_id, &override_disable, + &value_disable); + + /* + * Set the output value: + * 0: default + * 1: enabled + * 2: disabled + * 3: unknown (should not happen) + */ + if (override_disable && (value_disable == 1)) + *val = SLPC_PARAM_TASK_DISABLED; + else if (override_enable && (value_enable == 1)) + *val = SLPC_PARAM_TASK_ENABLED; + else if (!override_enable && !override_disable) + *val = SLPC_PARAM_TASK_DEFAULT; + else + *val = SLPC_PARAM_TASK_UNKNOWN; + + } else { + ret = -EINVAL; + } + + return ret; +} + void intel_slpc_init(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index bb06e6e..0faa5b4 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -235,6 +235,14 @@ struct slpc_param { extern struct slpc_param slpc_paramlist[]; extern const struct file_operations i915_slpc_param_ctl_fops; +extern const struct file_operations i915_slpc_gtperf_fops; +extern const struct file_operations i915_slpc_balancer_fops; +extern const struct file_operations i915_slpc_dcc_fops; + +#define SLPC_PARAM_TASK_DEFAULT 0 +#define SLPC_PARAM_TASK_ENABLED 1 +#define SLPC_PARAM_TASK_DISABLED 2 +#define SLPC_PARAM_TASK_UNKNOWN 3 /* intel_slpc.c */ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv, @@ -247,6 +255,10 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id, int *overriding, u32 *value); int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val); int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val); +int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val, + u32 enable_id, u32 disable_id); +int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val, + u32 enable_id, u32 disable_id); void intel_slpc_init(struct drm_i915_private *dev_priv); void intel_slpc_cleanup(struct drm_i915_private *dev_priv); void intel_slpc_enable(struct drm_i915_private *dev_priv);