From patchwork Wed Mar 22 23:27:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Taylor, Clinton A" X-Patchwork-Id: 9640245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EFABC601E9 for ; Wed, 22 Mar 2017 23:30:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D47E4281F9 for ; Wed, 22 Mar 2017 23:30:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C4B2D283F3; Wed, 22 Mar 2017 23:30:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 36D13281F9 for ; Wed, 22 Mar 2017 23:30:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FC3B6E9B6; Wed, 22 Mar 2017 23:30:05 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5843C6E9B6 for ; Wed, 22 Mar 2017 23:30:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490225404; x=1521761404; h=from:to:cc:subject:date:message-id; bh=2ACd3Mc3ckAYiItH3hwRic3IztwevatuxW3Nt4NrPRA=; b=oruYYt1L1WqRfOzmccpEG/j07zWMNR3bByQOyRq0MQbkfauo0POrV9kn 4/zzC1vSR4W9emA0uEnbuMPKr7Anrg==; Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2017 16:30:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,206,1486454400"; d="scan'208";a="78369951" Received: from cataylo2-ubuntu64-12.jf.intel.com ([10.7.199.52]) by orsmga005.jf.intel.com with ESMTP; 22 Mar 2017 16:30:03 -0700 From: clinton.a.taylor@intel.com To: Intel-gfx@lists.freedesktop.org Date: Wed, 22 Mar 2017 16:27:36 -0700 Message-Id: <1490225256-11667-1-git-send-email-clinton.a.taylor@intel.com> X-Mailer: git-send-email 1.7.9.5 Cc: Jani Nikula Subject: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Clint Taylor Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane signal if the Data Link N is greater than 0x80000. Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum value 20 bit instead of the maximum specification supported 24 bit value. Cc: Jani Nikula Cc: Anusha Srivatsa Signed-off-by: Clint Taylor Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04c8f69..838d8d5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4869,6 +4869,8 @@ enum { #define DATA_LINK_M_N_MASK (0xffffff) #define DATA_LINK_N_MAX (0x800000) +/* Maximum N value useable on some DP->HDMI converters */ +#define DATA_LINK_REDUCED_N_MAX (0x80000) #define _PIPEA_DATA_N_G4X 0x70054 #define _PIPEB_DATA_N_G4X 0x71054 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 010e5dd..6e1fdd2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6315,9 +6315,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, } static void compute_m_n(unsigned int m, unsigned int n, - uint32_t *ret_m, uint32_t *ret_n) + uint32_t *ret_m, uint32_t *ret_n, + uint32_t max_link_n) { - *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), max_link_n); *ret_m = div_u64((uint64_t) m * *ret_n, n); intel_reduce_m_n_ratio(ret_m, ret_n); } @@ -6327,14 +6328,20 @@ static void compute_m_n(unsigned int m, unsigned int n, int pixel_clock, int link_clock, struct intel_link_m_n *m_n) { + uint32_t max_link_n = DATA_LINK_N_MAX; m_n->tu = 64; + if ((nlanes==1) && (link_clock >= 540000)) + max_link_n = DATA_LINK_REDUCED_N_MAX; + compute_m_n(bits_per_pixel * pixel_clock, link_clock * nlanes * 8, - &m_n->gmch_m, &m_n->gmch_n); + &m_n->gmch_m, &m_n->gmch_n, + max_link_n); compute_m_n(pixel_clock, link_clock, - &m_n->link_m, &m_n->link_n); + &m_n->link_m, &m_n->link_n, + max_link_n); } static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)