From patchwork Thu Mar 23 23:11:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9642139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1EADE601E9 for ; Thu, 23 Mar 2017 23:07:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0198B28433 for ; Thu, 23 Mar 2017 23:07:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E65302845B; Thu, 23 Mar 2017 23:07:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7AA2728433 for ; Thu, 23 Mar 2017 23:07:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0650B6E2AD; Thu, 23 Mar 2017 23:07:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97ED46E2AD for ; Thu, 23 Mar 2017 23:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490310462; x=1521846462; h=from:to:cc:subject:date:message-id; bh=uyPBn0yuvquIQBONbDyAd0n+gRgMD6R4vS2Djg68XXY=; b=Q3E8NQWVjJSimsKiDTQYGp4JvOt/4M9l0irziWA+kusmSo6pyIOi5zDt YoL9cTLFLDImzswF59sMAbcRY/H2sA==; Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Mar 2017 16:07:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,212,1486454400"; d="scan'208";a="64317212" Received: from labuser-z97x-ud5h.jf.intel.com ([10.7.199.62]) by orsmga002.jf.intel.com with ESMTP; 23 Mar 2017 16:07:38 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Mar 2017 16:11:32 -0700 Message-Id: <1490310692-24468-1-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.1.4 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Validate cached link rate and lane count before retraining X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Currently intel_dp_check_link_status() tries to retrain the link if Clock recovery or Channel EQ for any of the lanes indicated by intel_dp->lane_count is not set. However these values cached in intel_dp structure can be stale if link training has failed for these values during previous modeset. Or these values can get stale since we have now re read the DPCD registers or it can be 0 in case of connected boot case. This patch validates these values against the common_rates and max lane count values. This is absolutely required incase the common_rates or max lane count are now different due to link fallback. Cc: Ville Syrjala Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fd96a6c..51fa6b5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -295,6 +295,23 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp, return -1; } +static bool intel_dp_link_params_is_valid(struct intel_dp *intel_dp) +{ + int common_rates[DP_MAX_SUPPORTED_RATES]; + int link_rate_index; + + link_rate_index = intel_dp_link_rate_index(intel_dp, + common_rates, + intel_dp->link_rate); + if (link_rate_index < 0) + return false; + if (!intel_dp->lane_count || + (intel_dp->lane_count > intel_dp_max_lane_count(intel_dp))) + return false; + + return true; +} + int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, int link_rate, uint8_t lane_count) { @@ -4224,9 +4241,10 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) if (!to_intel_crtc(intel_encoder->base.crtc)->active) return; - /* FIXME: we need to synchronize this sort of stuff with hardware - * readout. Currently fast link training doesn't work on boot-up. */ - if (!intel_dp->lane_count) + /* Validate the cached values of intel_dp->link_rate and + * intel_dp->lane_count before attempting to retrain. + */ + if (!intel_dp_link_params_is_valid(intel_dp)) return; /* Retrain if Channel EQ or CR not ok */