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Fri, 24 Mar 2017 11:36:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2752C89C28; Fri, 24 Mar 2017 11:36:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8E9AA89C28 for ; Fri, 24 Mar 2017 11:36:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490355382; x=1521891382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Dlz+6LDuuSyqFUd7q+JpYeTzanmzkKt9imBh8NZ+lCc=; b=Rix3ahUdhqDzUYymjWQOlebthfyEncEJtnfoC+wEkW/X1nYaaHFDNT7+ b2/YKb5bEcaUYsAEO0RQA9RDg7AUaA==; Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Mar 2017 04:36:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,214,1486454400"; d="scan'208";a="70277066" Received: from intel-desktop.iind.intel.com ([10.223.82.55]) by orsmga004.jf.intel.com with ESMTP; 24 Mar 2017 04:36:20 -0700 From: Praveen Paneri To: intel-gfx@lists.freedesktop.org Date: Fri, 24 Mar 2017 17:12:44 +0530 Message-Id: <1490355764-17230-1-git-send-email-praveen.paneri@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Cc: Praveen Paneri , Paulo Zanoni Subject: [Intel-gfx] [PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When FBC is enabled for linear, legacy Y-tiled and Yf-tiled surfaces on gen9, the cfb stride must be programmed by SW as cfb_stride = ceiling[(at least plane width in pixels)/ (32 * compression limit factor)] * 8 v2: Minor fix for a build error v3: Fixed subject, register name and platform check (Ville) v4: Added WA details in comment (Paulo) Cc: Paulo Zanoni Cc: Ville Syrjälä Signed-off-by: Praveen Paneri --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04c8f69..4adf2e6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6504,6 +6504,9 @@ enum { #define GLK_CL1_PWR_DOWN (1 << 11) #define GLK_CL2_PWR_DOWN (1 << 12) +#define CHICKEN_MISC_4 _MMIO(0x4208c) +#define FBC_STRIDE_OVERRIDE (1<<13) + #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 #define HSW_FBCQ_DIS (1 << 22) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index ded2add..1183633 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) static void gen7_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache; u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; + /* Display WA #0529: skl, kbl, bxt, glk */ + if (IS_GEN9(dev_priv) && + i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) { + int cfb_stride = DIV_ROUND_UP(cache->plane.src_w, + (32 * threshold)) * 8; + I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride); + } + dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);