From patchwork Mon Apr 3 17:07:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jim.bride@linux.intel.com X-Patchwork-Id: 9660005 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A66160353 for ; Mon, 3 Apr 2017 17:09:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74DFF2849A for ; Mon, 3 Apr 2017 17:09:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68449284C2; Mon, 3 Apr 2017 17:09:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BFA772849A for ; Mon, 3 Apr 2017 17:09:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D7E36E03F; Mon, 3 Apr 2017 17:09:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5B8F6E03F for ; Mon, 3 Apr 2017 17:09:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491239391; x=1522775391; h=from:to:cc:subject:date:message-id; bh=nVGI76wUoKcYOueXGzTTNtHNKlbDBCKlJ/RwO157Qto=; b=TlqtQ1HTq99rkEt9cTVhEUH6WD/IFquC9+hVHqycCWsZPK5pQoCowBO0 DqSmYH5hrU77cRmTt8tJC61uqZV5Dw==; Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2017 10:09:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,271,1486454400"; d="scan'208"; a="1114921210" Received: from shiv.jf.intel.com ([10.54.75.141]) by orsmga001.jf.intel.com with ESMTP; 03 Apr 2017 10:09:51 -0700 From: Jim Bride To: intel-gfx@lists.freedesktop.org Date: Mon, 3 Apr 2017 10:07:55 -0700 Message-Id: <1491239275-8408-1-git-send-email-jim.bride@linux.intel.com> X-Mailer: git-send-email 2.7.4 Cc: Wayne Boyer , Rodrigo Vivi Subject: [Intel-gfx] [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On SKL+ there is a bit in SRD_CTL that software is not supposed to modify, but we currently clobber that bit when we enable PSR. In order to preserve the value of that bit, go ahead and read SRD_CTL and do a field-wise setting of the various bits that we need to initialize before writing the register back out. Additionally, go ahead and explicitly disable single-frame update since we aren't currently supporting it. Cc: Rodrigo Vivi Cc: Wayne Boyer Signed-off-by: Jim Bride --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_psr.c | 23 +++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11b12f4..54d39e4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3590,14 +3590,17 @@ enum { #define EDP_PSR_SKIP_AUX_EXIT (1<<12) #define EDP_PSR_TP1_TP2_SEL (0<<11) #define EDP_PSR_TP1_TP3_SEL (1<<11) +#define EDP_PSR_TP2_TP3_TIME_MASK (3<<8) #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) +#define EDP_PSR_TP1_TIME_MASK (0x3<<4) #define EDP_PSR_TP1_TIME_500us (0<<4) #define EDP_PSR_TP1_TIME_100us (1<<4) #define EDP_PSR_TP1_TIME_2500us (2<<4) #define EDP_PSR_TP1_TIME_0us (3<<4) +#define EDP_PSR_IDLE_FRAME_MASK (0xf<<0) #define EDP_PSR_IDLE_FRAME_SHIFT 0 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index c3780d0..a050859 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) * with the 5 or 6 idle patterns. */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); - uint32_t val = EDP_PSR_ENABLE; + uint32_t val = I915_READ(EDP_PSR_CTL); + val |= EDP_PSR_ENABLE; + + /* We always set the max sleep time to the maximum value, so + * no need to zero out the field first. + */ val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; + + val &= ~EDP_PSR_IDLE_FRAME_MASK; val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; + val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK; if (IS_HASWELL(dev_priv)) val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; - if (dev_priv->psr.link_standby) + if (dev_priv->psr.link_standby) { val |= EDP_PSR_LINK_STANDBY; + /* SFU should only be enabled with link standby, but for + * now we do not support it. */ + val &= ~BDW_PSR_SINGLE_FRAME; + } else { + val &= ~EDP_PSR_LINK_STANDBY; + val &= ~BDW_PSR_SINGLE_FRAME; + } + + val &= ~EDP_PSR_TP1_TIME_MASK; if (dev_priv->vbt.psr.tp1_wakeup_time > 5) val |= EDP_PSR_TP1_TIME_2500us; else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) @@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TIME_0us; + val &= ~EDP_PSR_TP2_TP3_TIME_MASK; if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR_TP2_TP3_TIME_2500us; else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) @@ -309,6 +327,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP2_TP3_TIME_0us; + val &= ~EDP_PSR_TP1_TP3_SEL; if (intel_dp_source_supports_hbr2(intel_dp) && drm_dp_tps3_supported(intel_dp->dpcd)) val |= EDP_PSR_TP1_TP3_SEL;