From patchwork Wed Apr 5 02:04:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chuanxiao.Dong" X-Patchwork-Id: 9662829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 729BA6021C for ; Wed, 5 Apr 2017 02:06:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 620712823E for ; Wed, 5 Apr 2017 02:06:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 55D122851F; Wed, 5 Apr 2017 02:06:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B01332823E for ; Wed, 5 Apr 2017 02:06:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 402636E6F3; Wed, 5 Apr 2017 02:06:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B4176E6F3; Wed, 5 Apr 2017 02:06:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491358005; x=1522894005; h=from:to:cc:subject:date:message-id; bh=rcWEf5OSfgLd5QP8z1LH4AitpQarP5uhZ5jiP+Xx6ok=; b=x2iiYO0OmoP81/UuePOSXm9zaMHndY3fFDmsryOGsZpjO7gTmAH6eIT7 0CI8c869EAM7fqi4OdWbgVz1LRxKag==; Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Apr 2017 19:06:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,276,1486454400"; d="scan'208";a="84471221" Received: from cxdong-dell-dev.bj.intel.com ([10.238.154.60]) by fmsmga005.fm.intel.com with ESMTP; 04 Apr 2017 19:06:43 -0700 From: Chuanxiao Dong To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Apr 2017 10:04:59 +0800 Message-Id: <1491357900-3862-2-git-send-email-chuanxiao.dong@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491357900-3862-1-git-send-email-chuanxiao.dong@intel.com> References: <1491357900-3862-1-git-send-email-chuanxiao.dong@intel.com> In-Reply-To: <1490665792-5544-1-git-send-email-chuanxiao.dong@intel.com> References: <1490665792-5544-1-git-send-email-chuanxiao.dong@intel.com> Cc: intel-gvt-dev@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 1/2] drm/i915/scheduler: add gvt force-single-submission for guc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GVT needs single submission and cannot allow merge. So when GuC submitting a GVT request, the next one should be submitted to guc later until the previous one is completed. This is following the usage when using execlist mode submission. v2: make force-single-submission specific to gvt (Chris) v3: keep the original code implementation (Chris) Cc: chris@chris-wilson.co.uk Signed-off-by: Chuanxiao Dong --- drivers/gpu/drm/i915/i915_gem_context.h | 13 +++++++++++++ drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++++- drivers/gpu/drm/i915/intel_gvt.h | 11 +++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 25 ++++--------------------- 4 files changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 4af2ab94..2c3afec 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -246,6 +246,19 @@ static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx) return !ctx->file_priv; } +static inline bool +i915_gem_context_can_merge(const struct i915_gem_context *prev, + const struct i915_gem_context *next) +{ + if (prev != next) + return false; + + if (i915_gem_context_force_single_submission(prev)) + return false; + + return true; +} + /* i915_gem_context.c */ int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv); void i915_gem_context_lost(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 1642fff..862f4fd 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -668,10 +668,14 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine) struct drm_i915_gem_request *rq = rb_entry(rb, typeof(*rq), priotree.node); - if (last && rq->ctx != last->ctx) { + if (last && !i915_gem_context_can_merge(last->ctx, rq->ctx)) { if (port != engine->execlist_port) break; + if (intel_gvt_context_single_port_submit(last->ctx) || + intel_gvt_context_single_port_submit(rq->ctx)) + break; + i915_gem_request_assign(&port->request, last); nested_enable_signaling(last); port++; diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h index 25df2d6..c0dcd66 100644 --- a/drivers/gpu/drm/i915/intel_gvt.h +++ b/drivers/gpu/drm/i915/intel_gvt.h @@ -32,6 +32,12 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv); int intel_gvt_init_device(struct drm_i915_private *dev_priv); void intel_gvt_clean_device(struct drm_i915_private *dev_priv); int intel_gvt_init_host(void); + +static inline bool +intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx) +{ + return i915_gem_context_force_single_submission(ctx); +} #else static inline int intel_gvt_init(struct drm_i915_private *dev_priv) { @@ -40,6 +46,11 @@ static inline int intel_gvt_init(struct drm_i915_private *dev_priv) static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv) { } +static inline bool +intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx) +{ + return false; +} #endif #endif /* _INTEL_GVT_H_ */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0dc1cc4..61291e9 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -377,24 +377,6 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) writel(lower_32_bits(desc[0]), elsp); } -static bool ctx_single_port_submission(const struct i915_gem_context *ctx) -{ - return (IS_ENABLED(CONFIG_DRM_I915_GVT) && - i915_gem_context_force_single_submission(ctx)); -} - -static bool can_merge_ctx(const struct i915_gem_context *prev, - const struct i915_gem_context *next) -{ - if (prev != next) - return false; - - if (ctx_single_port_submission(prev)) - return false; - - return true; -} - static void execlists_dequeue(struct intel_engine_cs *engine) { struct drm_i915_gem_request *last; @@ -450,7 +432,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * request, and so we never need to tell the hardware about * the first. */ - if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { + if (last && + !i915_gem_context_can_merge(last->ctx, cursor->ctx)) { /* If we are on the second port and cannot combine * this request with the last, then we are done. */ @@ -463,8 +446,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * context (even though a different request) to * the second port. */ - if (ctx_single_port_submission(last->ctx) || - ctx_single_port_submission(cursor->ctx)) + if (intel_gvt_context_single_port_submit(last->ctx) || + intel_gvt_context_single_port_submit(cursor->ctx)) break; GEM_BUG_ON(last->ctx == cursor->ctx);