| Message ID | 1491506163-14587-12-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 04/06/2017 07:15 PM, Rodrigo Vivi wrote: > Let's inherit workarounds from previous platforms that > according to wa_database and BSpec are still valid for > Cannonlake. > > v2: Add missed workarounds. > v3: Rebase > > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 6 +++++ > drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_lrc.c | 1 + > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++----- > 5 files changed, 73 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 8bab4ae..3c8457d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > * called on driver load and after a GPU reset, so you can place > * workarounds here even if they get overwritten by GPU reset. > */ > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */ > if (IS_BROADWELL(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > - else if (IS_GEN9_BC(dev_priv)) > + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > else if (IS_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index efbbeb8..a09a0d7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3424,6 +3424,12 @@ enum { > #define PWM1_GATING_DIS (1 << 13) > > /* > + * GEN10 clock gating regs > + */ > +#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) > +#define SARBUNIT_CLKGATE_DIS (1 << 5) > + > +/* > * Display engine regs > */ > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 854e8e0..da819a7 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) > return 0; > } > > +static int cnl_init_workarounds(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *dev_priv = engine->i915; > + int ret; > + > + /* WaInPlaceDecompressionHang:cnl */ > + WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, > + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); > + > + /* WaEnablePreemptionGranularityControlByUMD:cnl */ > + ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); > + if (ret) > + return ret; > + > + /* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) { > + ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > static int kbl_init_workarounds(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > @@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine) > err = kbl_init_workarounds(engine); > else if (IS_GEMINILAKE(dev_priv)) > err = glk_init_workarounds(engine); > + else if (IS_CANNONLAKE(dev_priv)) > + err = cnl_init_workarounds(engine); > else > err = 0; > if (err) > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 0dc1cc4..23e2bed 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) > return -EINVAL; > > switch (INTEL_GEN(engine->i915)) { > + case 10: Are you sure this is what you want? gen9_init_perctx_bb is just an empty batchbuffer, but gen9_init_indirectctx_bb introduces some WAs that do not apply to CNL (WaFlushCoherentL3CacheLinesAtContextSwitch, WaClearSlmSpaceAtContextSwitch, etc...) > case 9: > wa_bb_fn[0] = gen9_init_indirectctx_bb; > wa_bb_fn[1] = gen9_init_perctx_bb; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 55e1e88..b6ecab9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -58,24 +58,24 @@ > > static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ > + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */ > I915_WRITE(CHICKEN_PAR1_1, > I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); > > I915_WRITE(GEN8_CONFIG0, > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > - /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */ > I915_WRITE(GEN8_CHICKEN_DCPR_1, > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > - /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > + /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */ > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */ > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS | > DISP_FBC_MEMORY_WAKE); > > - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ > + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */ > I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > ILK_DPFC_DISABLE_DUMMY0); > } > @@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) > > static void gen9_disable_rc6(struct drm_i915_private *dev_priv) > { > + gen9_init_clock_gating(dev_priv); > + > I915_WRITE(GEN6_RC_CONTROL, 0); > I915_WRITE(GEN9_PG_ENABLE, 0); > + > + /* WaDisableGamClockGating:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) > + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | > + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); > + > + /* WaFbcNukeOnHostModify:cnl */ > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); > } > > static void gen9_disable_rps(struct drm_i915_private *dev_priv) > @@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, > I915_WRITE(GEN7_MISCCPCTL, misccpctl); > } > > +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv) > +{ > + gen9_init_clock_gating(dev_priv); > + > + /* WaDisableGamClockGating:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) > + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | > + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); > + > + /* WaFbcNukeOnHostModify:cnl */ > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); > + > + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) > + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | > + SARBUNIT_CLKGATE_DIS); > +} > + > static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) > { > gen9_init_clock_gating(dev_priv); > @@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) > */ > void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > { > - if (IS_SKYLAKE(dev_priv)) > + if (IS_CANNONLAKE(dev_priv)) > + dev_priv->display.init_clock_gating = cannonlake_init_clock_gating; > + else if (IS_SKYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = skylake_init_clock_gating; > else if (IS_KABYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote: > Let's inherit workarounds from previous platforms that > according to wa_database and BSpec are still valid for > Cannonlake. > > v2: Add missed workarounds. > v3: Rebase > > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 6 +++++ > drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_lrc.c | 1 + > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++----- > 5 files changed, 73 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 8bab4ae..3c8457d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > * called on driver load and after a GPU reset, so you can place > * workarounds here even if they get overwritten by GPU reset. > */ > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */ > if (IS_BROADWELL(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > - else if (IS_GEN9_BC(dev_priv)) > + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > else if (IS_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index efbbeb8..a09a0d7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3424,6 +3424,12 @@ enum { > #define PWM1_GATING_DIS (1 << 13) > > /* > + * GEN10 clock gating regs > + */ > +#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) > +#define SARBUNIT_CLKGATE_DIS (1 << 5) > + > +/* > * Display engine regs > */ > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 854e8e0..da819a7 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) > return 0; > } > > +static int cnl_init_workarounds(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *dev_priv = engine->i915; > + int ret; > + > + /* WaInPlaceDecompressionHang:cnl */ > + WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, > + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); > + > + /* WaEnablePreemptionGranularityControlByUMD:cnl */ > + ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); > + if (ret) > + return ret; > + > + /* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) { > + ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > static int kbl_init_workarounds(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > @@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine) > err = kbl_init_workarounds(engine); > else if (IS_GEMINILAKE(dev_priv)) > err = glk_init_workarounds(engine); > + else if (IS_CANNONLAKE(dev_priv)) > + err = cnl_init_workarounds(engine); > else > err = 0; > if (err) > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 0dc1cc4..23e2bed 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) > return -EINVAL; > > switch (INTEL_GEN(engine->i915)) { > + case 10: > case 9: > wa_bb_fn[0] = gen9_init_indirectctx_bb; > wa_bb_fn[1] = gen9_init_perctx_bb; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 55e1e88..b6ecab9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -58,24 +58,24 @@ > > static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ > + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */ > I915_WRITE(CHICKEN_PAR1_1, > I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); > > I915_WRITE(GEN8_CONFIG0, > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > - /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */ > I915_WRITE(GEN8_CHICKEN_DCPR_1, > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > - /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > + /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */ > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */ > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS | > DISP_FBC_MEMORY_WAKE); > > - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ > + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */ > I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > ILK_DPFC_DISABLE_DUMMY0); > } > @@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) > > static void gen9_disable_rc6(struct drm_i915_private *dev_priv) > { > + gen9_init_clock_gating(dev_priv); > + This may be called from i915_drm_resume_early() through intel_uncore_sanitize() intel_sanitize_gt_powersave() intel_disable_gt_powersave() at which point power wells haven't been initialized yet. This may cause problems at least with ILK_DPFC_CHICKEN registers, which requires power well 1 in gen9 devices. Ander > I915_WRITE(GEN6_RC_CONTROL, 0); > I915_WRITE(GEN9_PG_ENABLE, 0); > + > + /* WaDisableGamClockGating:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) > + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | > + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); > + > + /* WaFbcNukeOnHostModify:cnl */ > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); > } > > static void gen9_disable_rps(struct drm_i915_private *dev_priv) > @@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, > I915_WRITE(GEN7_MISCCPCTL, misccpctl); > } > > +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv) > +{ > + gen9_init_clock_gating(dev_priv); > + > + /* WaDisableGamClockGating:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) > + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | > + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); > + > + /* WaFbcNukeOnHostModify:cnl */ > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); > + > + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ > + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) > + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | > + SARBUNIT_CLKGATE_DIS); > +} > + > static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) > { > gen9_init_clock_gating(dev_priv); > @@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) > */ > void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > { > - if (IS_SKYLAKE(dev_priv)) > + if (IS_CANNONLAKE(dev_priv)) > + dev_priv->display.init_clock_gating = cannonlake_init_clock_gating; > + else if (IS_SKYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = skylake_init_clock_gating; > else if (IS_KABYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 8bab4ae..3c8457d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */ if (IS_BROADWELL(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); - else if (IS_GEN9_BC(dev_priv)) + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index efbbeb8..a09a0d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3424,6 +3424,12 @@ enum { #define PWM1_GATING_DIS (1 << 13) /* + * GEN10 clock gating regs + */ +#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) +#define SARBUNIT_CLKGATE_DIS (1 << 5) + +/* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 854e8e0..da819a7 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) return 0; } +static int cnl_init_workarounds(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + int ret; + + /* WaInPlaceDecompressionHang:cnl */ + WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); + + /* WaEnablePreemptionGranularityControlByUMD:cnl */ + ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); + if (ret) + return ret; + + /* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) { + ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); + if (ret) + return ret; + } + + return 0; +} + static int kbl_init_workarounds(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine) err = kbl_init_workarounds(engine); else if (IS_GEMINILAKE(dev_priv)) err = glk_init_workarounds(engine); + else if (IS_CANNONLAKE(dev_priv)) + err = cnl_init_workarounds(engine); else err = 0; if (err) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0dc1cc4..23e2bed 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) return -EINVAL; switch (INTEL_GEN(engine->i915)) { + case 10: case 9: wa_bb_fn[0] = gen9_init_indirectctx_bb; wa_bb_fn[1] = gen9_init_perctx_bb; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 55e1e88..b6ecab9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -58,24 +58,24 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) { - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */ I915_WRITE(CHICKEN_PAR1_1, I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); - /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ - /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ + /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */ + /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */ I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE); - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); } @@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) static void gen9_disable_rc6(struct drm_i915_private *dev_priv) { + gen9_init_clock_gating(dev_priv); + I915_WRITE(GEN6_RC_CONTROL, 0); I915_WRITE(GEN9_PG_ENABLE, 0); + + /* WaDisableGamClockGating:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); + + /* WaFbcNukeOnHostModify:cnl */ + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); } static void gen9_disable_rps(struct drm_i915_private *dev_priv) @@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, I915_WRITE(GEN7_MISCCPCTL, misccpctl); } +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen9_init_clock_gating(dev_priv); + + /* WaDisableGamClockGating:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | + GEN6_GAMUNIT_CLOCK_GATE_DISABLE); + + /* WaFbcNukeOnHostModify:cnl */ + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); + + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | + SARBUNIT_CLKGATE_DIS); +} + static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) { gen9_init_clock_gating(dev_priv); @@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_SKYLAKE(dev_priv)) + if (IS_CANNONLAKE(dev_priv)) + dev_priv->display.init_clock_gating = cannonlake_init_clock_gating; + else if (IS_SKYLAKE(dev_priv)) dev_priv->display.init_clock_gating = skylake_init_clock_gating; else if (IS_KABYLAKE(dev_priv)) dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
Let's inherit workarounds from previous platforms that according to wa_database and BSpec are still valid for Cannonlake. v2: Add missed workarounds. v3: Rebase Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 6 +++++ drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++----- 5 files changed, 73 insertions(+), 8 deletions(-)