| Message ID | 1491506163-14587-33-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote: > From: "Kahola, Mika" <mika.kahola@intel.com> > > DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these > definitions when computing dpll's for ddi ports. > > v2: (Rodrigo) Remove register that was defined in another patch with > fixed name and more bits. > > Signed-off-by: Kahola, Mika <mika.kahola@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 87d2822..4d0ae98 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8850,6 +8850,22 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, > return 0; > } > > +static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, > + enum port port, > + struct intel_crtc_state *pipe_config) > +{ > + enum intel_dpll_id id; > + u32 temp; > + > + temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); > + id = temp >> (port * 2); Maybe use DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT which was defined in the previous patch? Also, might make sense to squash this with the next patch, but anyway, Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> > + > + if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) > + return; > + > + pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); > +} > + > static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, > enum port port, > struct intel_crtc_state *pipe_config) > @@ -9037,7 +9053,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > > port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; > > - if (IS_GEN9_BC(dev_priv)) > + if (IS_CANNONLAKE(dev_priv)) > + cannonlake_get_ddi_pll(dev_priv, port, pipe_config); > + else if (IS_GEN9_BC(dev_priv)) > skylake_get_ddi_pll(dev_priv, port, pipe_config); > else if (IS_GEN9_LP(dev_priv)) > bxt_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 87d2822..4d0ae98 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8850,6 +8850,22 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, return 0; } +static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, + enum port port, + struct intel_crtc_state *pipe_config) +{ + enum intel_dpll_id id; + u32 temp; + + temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); + id = temp >> (port * 2); + + if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) + return; + + pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); +} + static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) @@ -9037,7 +9053,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; - if (IS_GEN9_BC(dev_priv)) + if (IS_CANNONLAKE(dev_priv)) + cannonlake_get_ddi_pll(dev_priv, port, pipe_config); + else if (IS_GEN9_BC(dev_priv)) skylake_get_ddi_pll(dev_priv, port, pipe_config); else if (IS_GEN9_LP(dev_priv)) bxt_get_ddi_pll(dev_priv, port, pipe_config);