Message ID | 1491506163-14587-55-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > They're slightly different than the gen 9 calculations. I missed this at first, but GLK should follow the gen10 watermark programming as it has a gen10 display. > > TODO: before upstraming this, check if the spec is still the same. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++------- > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 0194d55..b07369a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3692,8 +3692,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > * should allow pixel_rate up to ~2 GHz which seems sufficient since max > * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. > */ > -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, > - uint32_t latency) > +static uint_fixed_16_16_t > +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, > + uint8_t cpp, uint32_t latency) > { > uint32_t wm_intermediate_val; > uint_fixed_16_16_t ret; > @@ -3703,6 +3704,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, > > wm_intermediate_val = latency * pixel_rate * cpp; > ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512); > + > + if (INTEL_GEN(dev_priv) >= 10) || IS_GLK > + ret.val += 1 << 16; > + > return ret; > } > > @@ -3836,11 +3841,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > > plane_bytes_per_line = width * cpp; > if (y_tiled) { > - interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * > - y_min_scanlines, 512); > + interm_pbpl = plane_bytes_per_line * y_min_scanlines; > + > + if (INTEL_GEN(dev_priv) >= 10) > + interm_pbpl++; > + > + interm_pbpl = DIV_ROUND_UP(interm_pbpl, 512); If I'm reading the spec right, the +1 should be done after the division by 512. > plane_blocks_per_line = > fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines); > - } else if (x_tiled) { > + } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { && !IS_GLK > interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); > plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); > } else { > @@ -3848,7 +3857,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); > } > > - method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); > + method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); > method2 = skl_wm_method2(plane_pixel_rate, > cstate->base.adjusted_mode.crtc_htotal, > latency, > @@ -3865,7 +3874,11 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > selected_result = method2; > else if ((ddb_allocation / > fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1) > - selected_result = min_fixed_16_16(method1, method2); > + if (INTEL_GEN(dev_priv) == 9) && !IS_GLK > + selected_result = min_fixed_16_16(method1, > + method2); > + else > + selected_result = method2; > else > selected_result = method1; > }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0194d55..b07369a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3692,8 +3692,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. */ -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, - uint32_t latency) +static uint_fixed_16_16_t +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, + uint8_t cpp, uint32_t latency) { uint32_t wm_intermediate_val; uint_fixed_16_16_t ret; @@ -3703,6 +3704,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, wm_intermediate_val = latency * pixel_rate * cpp; ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512); + + if (INTEL_GEN(dev_priv) >= 10) + ret.val += 1 << 16; + return ret; } @@ -3836,11 +3841,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_bytes_per_line = width * cpp; if (y_tiled) { - interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * - y_min_scanlines, 512); + interm_pbpl = plane_bytes_per_line * y_min_scanlines; + + if (INTEL_GEN(dev_priv) >= 10) + interm_pbpl++; + + interm_pbpl = DIV_ROUND_UP(interm_pbpl, 512); plane_blocks_per_line = fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines); - } else if (x_tiled) { + } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); } else { @@ -3848,7 +3857,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); } - method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); + method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); method2 = skl_wm_method2(plane_pixel_rate, cstate->base.adjusted_mode.crtc_htotal, latency, @@ -3865,7 +3874,11 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, selected_result = method2; else if ((ddb_allocation / fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1) - selected_result = min_fixed_16_16(method1, method2); + if (INTEL_GEN(dev_priv) == 9) + selected_result = min_fixed_16_16(method1, + method2); + else + selected_result = method2; else selected_result = method1; }