| Message ID | 1491905472-16189-1-git-send-email-oscar.mateo@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Apr 11, 2017 at 03:11:12AM -0700, Oscar Mateo wrote: > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Technically speaking, the context size is per engine class, not per > instance. > > v2: Add MISSING_CASE (Tvrtko) > > v3: Rebased > > v4: Restore the interface back to hiding the class lookup (Chris) > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 26 +++++++++++++++++--------- > 1 file changed, 17 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 0dc1cc4..3921566 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1923,23 +1923,31 @@ static void execlists_init_reg_state(u32 *regs, > */ > uint32_t intel_lr_context_size(struct intel_engine_cs *engine) > { > + struct drm_i915_private *dev_priv = engine->i915; > int ret = 0; > > - WARN_ON(INTEL_GEN(engine->i915) < 8); > + WARN_ON(INTEL_GEN(dev_priv) < 8); > > - switch (engine->id) { > - case RCS: > - if (INTEL_GEN(engine->i915) >= 9) > + switch (engine->class) { > + case RENDER_CLASS: > + switch (INTEL_GEN(dev_priv)) { > + default: > + MISSING_CASE(INTEL_GEN(dev_priv)); > + case 9: > ret = GEN9_LR_CONTEXT_RENDER_SIZE; > - else > + break; > + case 8: > ret = GEN8_LR_CONTEXT_RENDER_SIZE; > + break; > + } > break; > - case VCS: > - case BCS: > - case VECS: > - case VCS2: > + case VIDEO_DECODE_CLASS: > + case VIDEO_ENHANCEMENT_CLASS: > + case COPY_ENGINE_CLASS: > ret = GEN8_LR_CONTEXT_OTHER_SIZE; > break; > + default: > + MISSING_CASE(engine->class); Sorry, couldn't resist moving this MISSING_CASE so that both switches were consistent in style. Thanks for the patch, pushed. Better update the igt names again... -Chris
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0dc1cc4..3921566 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1923,23 +1923,31 @@ static void execlists_init_reg_state(u32 *regs, */ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) { + struct drm_i915_private *dev_priv = engine->i915; int ret = 0; - WARN_ON(INTEL_GEN(engine->i915) < 8); + WARN_ON(INTEL_GEN(dev_priv) < 8); - switch (engine->id) { - case RCS: - if (INTEL_GEN(engine->i915) >= 9) + switch (engine->class) { + case RENDER_CLASS: + switch (INTEL_GEN(dev_priv)) { + default: + MISSING_CASE(INTEL_GEN(dev_priv)); + case 9: ret = GEN9_LR_CONTEXT_RENDER_SIZE; - else + break; + case 8: ret = GEN8_LR_CONTEXT_RENDER_SIZE; + break; + } break; - case VCS: - case BCS: - case VECS: - case VCS2: + case VIDEO_DECODE_CLASS: + case VIDEO_ENHANCEMENT_CLASS: + case COPY_ENGINE_CLASS: ret = GEN8_LR_CONTEXT_OTHER_SIZE; break; + default: + MISSING_CASE(engine->class); } return ret;