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[3/4] drm/i915/scheduler: add gvt force-single-submission for guc

Message ID 1492666754-8135-2-git-send-email-chuanxiao.dong@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chuanxiao.Dong April 20, 2017, 5:39 a.m. UTC 
GVT needs single submission and cannot allow merge. So when GuC submitting
a GVT request, the next one should be submitted to guc later until the
previous one is completed. This is following the usage when using execlist
mode submission.

Cc: chris@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 1642fff..862f4fd 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -668,10 +668,14 @@  static bool i915_guc_dequeue(struct intel_engine_cs *engine)
 		struct drm_i915_gem_request *rq =
 			rb_entry(rb, typeof(*rq), priotree.node);
 
-		if (last && rq->ctx != last->ctx) {
+		if (last && !i915_gem_context_can_merge(last->ctx, rq->ctx)) {
 			if (port != engine->execlist_port)
 				break;
 
+			if (intel_gvt_context_single_port_submit(last->ctx) ||
+				intel_gvt_context_single_port_submit(rq->ctx))
+				break;
+
 			i915_gem_request_assign(&port->request, last);
 			nested_enable_signaling(last);
 			port++;