diff mbox

[4/4] drm/i915/scheduler: add gvt notification for guc

Message ID 1492666754-8135-3-git-send-email-chuanxiao.dong@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chuanxiao.Dong April 20, 2017, 5:39 a.m. UTC 
GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Cc: xiao.zheng@intel.com
Cc: kevin.tian@intel.com
Cc: joonas.lahtinen@linux.intel.com
Cc: chris@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 862f4fd..2f3bb16 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@  static void __i915_guc_submit(struct drm_i915_gem_request *rq)
 	unsigned long flags;
 	int b_ret;
 
+	intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
 	/* WA to flush out the pending GMADR writes to ring buffer. */
 	if (i915_vma_is_map_and_fenceable(rq->ring->vma))
 		POSTING_READ_FW(GUC_STATUS);
@@ -712,6 +714,8 @@  static void i915_guc_irq_handler(unsigned long data)
 		rq = port[0].request;
 		while (rq && i915_gem_request_completed(rq)) {
 			trace_i915_gem_request_out(rq);
+			intel_gvt_notify_context_status(rq,
+					INTEL_CONTEXT_SCHEDULE_OUT);
 			i915_gem_request_put(rq);
 			port[0].request = port[1].request;
 			port[1].request = NULL;