| Message ID | 1496181187-13514-6-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Jani, Daniel, could I merge the 5 patches already after CI respond? I rebased and retest here on CNL.... But I'd like to start merging so we unblock CFL as well, maybe on top of this CNP before CNL... Jani, also I believe you would be the best reviewer for this 6th patch here, could you please consider taking a look? Thanks, Rodrigo. On Tue, May 30, 2017 at 2:53 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > As for BXT, PP_DIVISOR was removed from CNP PCH and power > cycle delay has been moved to PP_CONTROL. > > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 58dca87..1a27c72 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv, > regs->pp_stat = PP_STATUS(pps_idx); > regs->pp_on = PP_ON_DELAYS(pps_idx); > regs->pp_off = PP_OFF_DELAYS(pps_idx); > - if (!IS_GEN9_LP(dev_priv)) > + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) > regs->pp_div = PP_DIVISOR(pps_idx); > } > > @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) > > pp_on = I915_READ(regs.pp_on); > pp_off = I915_READ(regs.pp_off); > - if (!IS_GEN9_LP(dev_priv)) { > + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) { > I915_WRITE(regs.pp_ctrl, pp_ctl); > pp_div = I915_READ(regs.pp_div); > } > @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > PANEL_POWER_DOWN_DELAY_SHIFT; > > - if (IS_GEN9_LP(dev_priv)) { > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > BXT_POWER_CYCLE_DELAY_SHIFT; > if (tmp > 0) > @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); > /* Compute the divisor for the pp clock, simply match the Bspec > * formula. */ > - if (IS_GEN9_LP(dev_priv)) { > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > pp_div = I915_READ(regs.pp_ctrl); > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; > pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) > @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", > I915_READ(regs.pp_on), > I915_READ(regs.pp_off), > - IS_GEN9_LP(dev_priv) ? > + (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ? > (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : > I915_READ(regs.pp_div)); > } > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 58dca87..1a27c72 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv, regs->pp_stat = PP_STATUS(pps_idx); regs->pp_on = PP_ON_DELAYS(pps_idx); regs->pp_off = PP_OFF_DELAYS(pps_idx); - if (!IS_GEN9_LP(dev_priv)) + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) regs->pp_div = PP_DIVISOR(pps_idx); } @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) pp_on = I915_READ(regs.pp_on); pp_off = I915_READ(regs.pp_off); - if (!IS_GEN9_LP(dev_priv)) { + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) { I915_WRITE(regs.pp_ctrl, pp_ctl); pp_div = I915_READ(regs.pp_div); } @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> PANEL_POWER_DOWN_DELAY_SHIFT; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> BXT_POWER_CYCLE_DELAY_SHIFT; if (tmp > 0) @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); /* Compute the divisor for the pp clock, simply match the Bspec * formula. */ - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { pp_div = I915_READ(regs.pp_ctrl); pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", I915_READ(regs.pp_on), I915_READ(regs.pp_off), - IS_GEN9_LP(dev_priv) ? + (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ? (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : I915_READ(regs.pp_div)); }
As for BXT, PP_DIVISOR was removed from CNP PCH and power cycle delay has been moved to PP_CONTROL. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)