| Message ID | 1498073863-26343-1-git-send-email-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote: > According to the eDP spec the minimum value for panel power cycle delay > (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle > delay field should be programmed to "+1" value. Eg: To have a delay > of 500ms this should be programmed to 6. This patch fixes the write > by adding +1 to the pp_div value so it programs the correct min > required panel power cycle delay. > Since we program it to +1 value, when we perform HW readout, this > value should subtract 1 before verifying pps state. This patch makes > this correction as well to avoid "PPS state mismatch" error. > This patch also adds a case where if the readout is 0 for the first readout, > then read it as 0, dont subtract. > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index bca4ac1..089e373 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > struct intel_dp *intel_dp, struct edp_power_seq *seq) > { > u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; > + u16 pp_cycle_delay = 0; > struct pps_registers regs; > > intel_pps_get_registers(dev_priv, intel_dp, ®s); > @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > PANEL_POWER_DOWN_DELAY_SHIFT; > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) > + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > BXT_POWER_CYCLE_DELAY_SHIFT; > - if (tmp > 0) > - seq->t11_t12 = (tmp - 1) * 1000; > - else > - seq->t11_t12 = 0; > - } else { > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > - } > + else > + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > + PANEL_POWER_CYCLE_DELAY_SHIFT; > + if (pp_cycle_delay > 0) > + seq->t11_t12 = (pp_cycle_delay - 1) * 1000; > + else > + seq->t11_t12 = 0; I think it's probably easier to go the other way and just add the +100 msec to the vbt delay, and nuke the BXT/CNP special casing in the code. > } > > static void > @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > << BXT_POWER_CYCLE_DELAY_SHIFT); > } else { > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000) > << PANEL_POWER_CYCLE_DELAY_SHIFT); > } > > -- > 2.1.4
On Wed, Jun 21, 2017 at 11:03:58PM +0300, Ville Syrjälä wrote: > On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote: > > According to the eDP spec the minimum value for panel power cycle delay > > (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle > > delay field should be programmed to "+1" value. Eg: To have a delay > > of 500ms this should be programmed to 6. This patch fixes the write > > by adding +1 to the pp_div value so it programs the correct min > > required panel power cycle delay. > > Since we program it to +1 value, when we perform HW readout, this > > value should subtract 1 before verifying pps state. This patch makes > > this correction as well to avoid "PPS state mismatch" error. > > This patch also adds a case where if the readout is 0 for the first readout, > > then read it as 0, dont subtract. > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Clint Taylor <Clinton.A.Taylor@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++----------- > > 1 file changed, 11 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index bca4ac1..089e373 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > > struct intel_dp *intel_dp, struct edp_power_seq *seq) > > { > > u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; > > + u16 pp_cycle_delay = 0; > > struct pps_registers regs; > > > > intel_pps_get_registers(dev_priv, intel_dp, ®s); > > @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > > PANEL_POWER_DOWN_DELAY_SHIFT; > > > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) > > + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > > BXT_POWER_CYCLE_DELAY_SHIFT; > > - if (tmp > 0) > > - seq->t11_t12 = (tmp - 1) * 1000; > > - else > > - seq->t11_t12 = 0; > > - } else { > > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > > - } > > + else > > + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > > + PANEL_POWER_CYCLE_DELAY_SHIFT; > > + if (pp_cycle_delay > 0) > > + seq->t11_t12 = (pp_cycle_delay - 1) * 1000; > > + else > > + seq->t11_t12 = 0; > > I think it's probably easier to go the other way and just add the +100 > msec to the vbt delay, and nuke the BXT/CNP special casing in the code. > The reason I am doing the -1 here is that this hw_readout gets called in intel_dp_pps_verify each time during edp_panel_on and it reads the values written into the register so lets say we wrote 6 into the register for 500ms then it will read 6 so we need to subtract 1 and multiply by 1000 to actually get 5000 that gets written into intel->pps_delays. Also keeping it at 5000 makes more sense because thats the number in edp spec. rather than (adding 100ms to 500) * 1000 so storing 6000. Manasi > > } > > > > static void > > @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > > << BXT_POWER_CYCLE_DELAY_SHIFT); > > } else { > > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > > + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000) > > << PANEL_POWER_CYCLE_DELAY_SHIFT); > > } > > > > -- > > 2.1.4 > > -- > Ville Syrjälä > Intel OTC
On Wed, Jun 21, 2017 at 06:32:09PM -0700, Manasi Navare wrote: > On Wed, Jun 21, 2017 at 11:03:58PM +0300, Ville Syrjälä wrote: > > On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote: > > > According to the eDP spec the minimum value for panel power cycle delay > > > (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle > > > delay field should be programmed to "+1" value. Eg: To have a delay > > > of 500ms this should be programmed to 6. This patch fixes the write > > > by adding +1 to the pp_div value so it programs the correct min > > > required panel power cycle delay. > > > Since we program it to +1 value, when we perform HW readout, this > > > value should subtract 1 before verifying pps state. This patch makes > > > this correction as well to avoid "PPS state mismatch" error. > > > This patch also adds a case where if the readout is 0 for the first readout, > > > then read it as 0, dont subtract. > > > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > > Cc: Clint Taylor <Clinton.A.Taylor@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++----------- > > > 1 file changed, 11 insertions(+), 11 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > > index bca4ac1..089e373 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > > > struct intel_dp *intel_dp, struct edp_power_seq *seq) > > > { > > > u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; > > > + u16 pp_cycle_delay = 0; > > > struct pps_registers regs; > > > > > > intel_pps_get_registers(dev_priv, intel_dp, ®s); > > > @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, > > > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > > > PANEL_POWER_DOWN_DELAY_SHIFT; > > > > > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > > > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) > > > + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > > > BXT_POWER_CYCLE_DELAY_SHIFT; > > > - if (tmp > 0) > > > - seq->t11_t12 = (tmp - 1) * 1000; > > > - else > > > - seq->t11_t12 = 0; > > > - } else { > > > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > > > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > > > - } > > > + else > > > + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > > > + PANEL_POWER_CYCLE_DELAY_SHIFT; > > > + if (pp_cycle_delay > 0) > > > + seq->t11_t12 = (pp_cycle_delay - 1) * 1000; > > > + else > > > + seq->t11_t12 = 0; > > > > I think it's probably easier to go the other way and just add the +100 > > msec to the vbt delay, and nuke the BXT/CNP special casing in the code. > > > > The reason I am doing the -1 here is that this hw_readout gets called > in intel_dp_pps_verify each time during edp_panel_on and it reads the > values written into the register so lets say we wrote 6 into the register for > 500ms then it will read 6 so we need to subtract 1 and multiply by 1000 to actually > get 5000 that gets written into intel->pps_delays. We should just doe the /1000 *1000. The +1 is bogus and it's not there in the pre-BXT code. > > Also keeping it at 5000 makes more sense because thats the number in edp spec. > rather than (adding 100ms to 500) * 1000 so storing 6000. But that's what we do on most platforms. So IMO just go with it. > > Manasi > > > > } > > > > > > static void > > > @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > > > << BXT_POWER_CYCLE_DELAY_SHIFT); > > > } else { > > > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > > > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > > > + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000) > > > << PANEL_POWER_CYCLE_DELAY_SHIFT); > > > } > > > > > > -- > > > 2.1.4 > > > > -- > > Ville Syrjälä > > Intel OTC
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bca4ac1..089e373 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, struct intel_dp *intel_dp, struct edp_power_seq *seq) { u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; + u16 pp_cycle_delay = 0; struct pps_registers regs; intel_pps_get_registers(dev_priv, intel_dp, ®s); @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> PANEL_POWER_DOWN_DELAY_SHIFT; - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> BXT_POWER_CYCLE_DELAY_SHIFT; - if (tmp > 0) - seq->t11_t12 = (tmp - 1) * 1000; - else - seq->t11_t12 = 0; - } else { - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; - } + else + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> + PANEL_POWER_CYCLE_DELAY_SHIFT; + if (pp_cycle_delay > 0) + seq->t11_t12 = (pp_cycle_delay - 1) * 1000; + else + seq->t11_t12 = 0; } static void @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, << BXT_POWER_CYCLE_DELAY_SHIFT); } else { pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT); }
According to the eDP spec the minimum value for panel power cycle delay (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle delay field should be programmed to "+1" value. Eg: To have a delay of 500ms this should be programmed to 6. This patch fixes the write by adding +1 to the pp_div value so it programs the correct min required panel power cycle delay. Since we program it to +1 value, when we perform HW readout, this value should subtract 1 before verifying pps state. This patch makes this correction as well to avoid "PPS state mismatch" error. This patch also adds a case where if the readout is 0 for the first readout, then read it as 0, dont subtract. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Clint Taylor <Clinton.A.Taylor@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)