From patchwork Wed Jun 21 19:37:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9802795 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A187F60329 for ; Wed, 21 Jun 2017 19:32:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91A9728545 for ; Wed, 21 Jun 2017 19:32:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 860E82856F; Wed, 21 Jun 2017 19:32:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3FC3728563 for ; Wed, 21 Jun 2017 19:31:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB2A6E564; Wed, 21 Jun 2017 19:31:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 88E5F6E564 for ; Wed, 21 Jun 2017 19:31:57 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2017 12:31:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,370,1493708400"; d="scan'208";a="983652025" Received: from labuser-z97x-ud5h.jf.intel.com ([10.7.199.62]) by orsmga003.jf.intel.com with ESMTP; 21 Jun 2017 12:31:56 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Jun 2017 12:37:43 -0700 Message-Id: <1498073863-26343-1-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.1.4 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to the eDP spec the minimum value for panel power cycle delay (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle delay field should be programmed to "+1" value. Eg: To have a delay of 500ms this should be programmed to 6. This patch fixes the write by adding +1 to the pp_div value so it programs the correct min required panel power cycle delay. Since we program it to +1 value, when we perform HW readout, this value should subtract 1 before verifying pps state. This patch makes this correction as well to avoid "PPS state mismatch" error. This patch also adds a case where if the readout is 0 for the first readout, then read it as 0, dont subtract. Signed-off-by: Manasi Navare Cc: Ville Syrjala Cc: Clint Taylor --- drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bca4ac1..089e373 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, struct intel_dp *intel_dp, struct edp_power_seq *seq) { u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; + u16 pp_cycle_delay = 0; struct pps_registers regs; intel_pps_get_registers(dev_priv, intel_dp, ®s); @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> PANEL_POWER_DOWN_DELAY_SHIFT; - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> BXT_POWER_CYCLE_DELAY_SHIFT; - if (tmp > 0) - seq->t11_t12 = (tmp - 1) * 1000; - else - seq->t11_t12 = 0; - } else { - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; - } + else + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> + PANEL_POWER_CYCLE_DELAY_SHIFT; + if (pp_cycle_delay > 0) + seq->t11_t12 = (pp_cycle_delay - 1) * 1000; + else + seq->t11_t12 = 0; } static void @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, << BXT_POWER_CYCLE_DELAY_SHIFT); } else { pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT); }