From patchwork Tue Jul 18 21:34:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jim.bride@linux.intel.com X-Patchwork-Id: 9849571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5E79C600CC for ; Tue, 18 Jul 2017 21:36:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C887285DE for ; Tue, 18 Jul 2017 21:36:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41718285F7; Tue, 18 Jul 2017 21:36:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0CE4285DE for ; Tue, 18 Jul 2017 21:36:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E13C6E3C8; Tue, 18 Jul 2017 21:36:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8ADA36E11C for ; Tue, 18 Jul 2017 21:36:43 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jul 2017 14:36:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,378,1496127600"; d="scan'208";a="288527406" Received: from shiv.jf.intel.com ([10.54.75.141]) by fmsmga004.fm.intel.com with ESMTP; 18 Jul 2017 14:36:42 -0700 From: Jim Bride To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Jul 2017 14:34:05 -0700 Message-Id: <1500413648-4765-1-git-send-email-jim.bride@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499811596-14634-1-git-send-email-jim.bride@linux.intel.com> References: <1499811596-14634-1-git-send-email-jim.bride@linux.intel.com> Cc: Jani Nikula , Wayne Boyer , Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH v4 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On SKL+ there is a bit in SRD_CTL that software is not supposed to modify, but we currently clobber that bit when we enable PSR. In order to preserve the value of that bit, go ahead and read SRD_CTL and do a field-wise setting of the various bits that we need to initialize before writing the register back out. Additionally, go ahead and explicitly disable single-frame update since we aren't currently supporting it. v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we always set it to the max value. (Rodrigo) * Rebase v3-v4: * Rebase Cc: Rodrigo Vivi Cc: Paulo Zanoni Cc: Wayne Boyer Cc: Jani Nikula Reviewed-by: Rodrigo Vivi Signed-off-by: Jim Bride --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_psr.c | 21 +++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c712d01..3e62429 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3789,18 +3789,22 @@ enum { #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) +#define EDP_PSR_MAX_SLEEP_TIME_MASK (0x1f<<20) #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) #define EDP_PSR_TP1_TP2_SEL (0<<11) #define EDP_PSR_TP1_TP3_SEL (1<<11) +#define EDP_PSR_TP2_TP3_TIME_MASK (3<<8) #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) +#define EDP_PSR_TP1_TIME_MASK (0x3<<4) #define EDP_PSR_TP1_TIME_500us (0<<4) #define EDP_PSR_TP1_TIME_100us (1<<4) #define EDP_PSR_TP1_TIME_2500us (2<<4) #define EDP_PSR_TP1_TIME_0us (3<<4) +#define EDP_PSR_IDLE_FRAME_MASK (0xf<<0) #define EDP_PSR_IDLE_FRAME_SHIFT 0 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 559f1ab..132987b 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) * with the 5 or 6 idle patterns. */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); - uint32_t val = EDP_PSR_ENABLE; + uint32_t val = I915_READ(EDP_PSR_CTL); + val |= EDP_PSR_ENABLE; + + val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK; val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; + + val &= ~EDP_PSR_IDLE_FRAME_MASK; val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; + val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK; if (IS_HASWELL(dev_priv)) val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; - if (dev_priv->psr.link_standby) + if (dev_priv->psr.link_standby) { val |= EDP_PSR_LINK_STANDBY; + /* SFU should only be enabled with link standby, but for + * now we do not support it. */ + val &= ~BDW_PSR_SINGLE_FRAME; + } else { + val &= ~EDP_PSR_LINK_STANDBY; + val &= ~BDW_PSR_SINGLE_FRAME; + } + + val &= ~EDP_PSR_TP1_TIME_MASK; if (dev_priv->vbt.psr.tp1_wakeup_time > 5) val |= EDP_PSR_TP1_TIME_2500us; else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) @@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TIME_0us; + val &= ~EDP_PSR_TP2_TP3_TIME_MASK; if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR_TP2_TP3_TIME_2500us; else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) @@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP2_TP3_TIME_0us; + val &= ~EDP_PSR_TP1_TP3_SEL; if (intel_dp_source_supports_hbr2(intel_dp) && drm_dp_tps3_supported(intel_dp->dpcd)) val |= EDP_PSR_TP1_TP3_SEL;