From patchwork Wed Aug 23 01:49:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9915855 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 46561603F9 for ; Tue, 22 Aug 2017 17:50:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 272D02623D for ; Tue, 22 Aug 2017 17:50:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1ACD128899; Tue, 22 Aug 2017 17:50:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 70D432623D for ; Tue, 22 Aug 2017 17:50:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C25F6E3F3; Tue, 22 Aug 2017 17:50:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1BEA66E3F3; Tue, 22 Aug 2017 17:50:48 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 22 Aug 2017 10:50:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,413,1498546800"; d="scan'208";a="893068284" Received: from unknown (HELO zhiwang1-MOBL.ger.corp.intel.com) ([10.252.28.165]) by FMSMGA003.fm.intel.com with ESMTP; 22 Aug 2017 10:50:46 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Wed, 23 Aug 2017 09:49:30 +0800 Message-Id: <1503452970-31112-1-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [RFCv2 RESEND 2/3] drm/i915: Introduce private PAT management X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The private PAT management is to support both static and dynamic PPAT entry manipulation. During the initialization, the PPAT indexes with specific PPAT values could be reserved and set by intel_ppat_reserve. The unused PPAT entries can be allocated/freed later at runtime. Two APIs are introduced for dynamically managing PPAT entries: intel_ppat_get and intel_ppat_set. intel_ppat_get will search for an existing PPAT entry which perfectly matches the required PPAT value. If not, it will try to allocate or return a partially matched PPAT entry if there is any available PPAT indexes or not. intel_ppat_put will put back the PPAT entry which comes from intel_ppat_get. If it's dynamically allocated, the reference count will be decreased. If the reference count turns into zero, the PPAT index is freed again. Besides, another two callbacks are introduced to support the private PAT management framework. One is ppat->update(), which writes the PPAT configurations in ppat->entries into HW. Another one is ppat->match, which will return a score to show how two PPAT values match with each other. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem_gtt.c | 129 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 36 ++++++++++ 3 files changed, 167 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 60267e3..97b46f8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2307,6 +2307,8 @@ struct drm_i915_private { DECLARE_HASHTABLE(mm_structs, 7); struct mutex mm_lock; + struct intel_ppat ppat; + /* Kernel Modesetting */ struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 09d1d48..2a521b6 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2742,6 +2742,121 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return 0; } +/** + * intel_ppat_reserve - reserve a PPAT index and set the PPAT value + * @ppat: i915 PPAT instance + * @index: the PPAT index needs to be reserved + * @value: the PPAT value needs to be set + * + * A PPAT entry sits on the reserved PPAT index will not be modified by PPAT + * management. + */ +void intel_ppat_reserve(struct intel_ppat *ppat, unsigned int index, u8 value) +{ + GEM_BUG_ON(index >= ppat->max_entries); + GEM_BUG_ON(test_bit(index, ppat->reserved)); + + ppat->entries[index].value = value; + set_bit(index, ppat->reserved); + set_bit(index, ppat->used); +} + +/** + * intel_ppat_get - dynamically get a usable PPAT entry + * @dev_priv: i915 device instance + * @value: the PPAT value required by the caller + * + * The function tries to search if there is an existing PPAT entry which + * matches with the required value. If perfectly matched, the existing PPAT + * entry will be used. If only partially matched, it will try to check if + * there is any available PPAT index. If yes, it will allocate a new PPAT + * index for the required entry and update the HW. If not, the partially + * matched entry will be used. + */ +struct intel_ppat_entry *intel_ppat_get(struct drm_i915_private *dev_priv, + u8 value) +{ + struct intel_ppat *ppat = &dev_priv->ppat; + struct intel_ppat_entry *entry; + int i, used; + unsigned int score, best_score; + + score = best_score = 0; + used = 0; + + /* First, find a suitable value from available entries */ + for_each_set_bit(i, ppat->used, ppat->max_entries) { + score = ppat->match(ppat->entries[i].value, value); + /* Perfect match */ + if (score == ~0) { + entry = &ppat->entries[i]; + kref_get(&entry->ref_count); + return entry; + } + + if (score > best_score) { + entry = &ppat->entries[i]; + best_score = score; + } + used++; + } + + /* No matched entry and we can't allocate a new entry. */ + if (!best_score && used == ppat->max_entries) { + DRM_ERROR("Fail to get PPAT entry\n"); + return ERR_PTR(-ENOSPC); + } + + /* + * Found a matched entry which is not perfect, + * and we can't allocate a new entry. + */ + if (best_score && used == ppat->max_entries) { + kref_get(&entry->ref_count); + return entry; + } + + /* Allocate a new entry */ + i = find_first_zero_bit(ppat->used, ppat->max_entries); + set_bit(i, ppat->used); + + entry = &ppat->entries[i]; + entry->value = value; + kref_init(&entry->ref_count); + + ppat->update(dev_priv); + return entry; +} + +static void put_ppat(struct kref *kref) +{ + struct intel_ppat_entry *entry = + container_of(kref, struct intel_ppat_entry, ref_count); + struct intel_ppat *ppat = entry->ppat; + struct drm_i915_private *dev_priv = ppat->dev_priv; + int index = entry - ppat->entries; + + if (test_bit(index, ppat->reserved)) + return; + + entry->value = ppat->dummy_value; + clear_bit(index, ppat->used); + ppat->update(dev_priv); +} + +/** + * intel_ppat_put - put back the PPAT entry got from intel_ppat_get() + * @entry: an intel PPAT entry + * + * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the + * entry is dynamically allocated, its reference count will be decreased. Once + * the reference count becomes into zero, the PPAT index becomes free again. + */ +void intel_ppat_put(struct intel_ppat_entry *entry) +{ + kref_put(&entry->ref_count, put_ppat); +} + static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) { /* XXX: spec is unclear if this is still needed for CNL+ */ @@ -2843,12 +2958,26 @@ static void gen6_gmch_remove(struct i915_address_space *vm) static void setup_private_pat(struct drm_i915_private *dev_priv) { + struct intel_ppat *ppat = &dev_priv->ppat; + int i; + + ppat->dev_priv = dev_priv; + if (INTEL_GEN(dev_priv) >= 10) cnl_setup_private_ppat(dev_priv); else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); + + GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES); + + for_each_clear_bit(i, ppat->reserved, ppat->max_entries) { + ppat->entries[i].value = ppat->dummy_value; + ppat->entries[i].ppat = ppat; + } + + ppat->update(dev_priv); } static int gen8_gmch_probe(struct i915_ggtt *ggtt) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index b4e3aa7..eeb1307 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -536,6 +536,42 @@ i915_vm_to_ggtt(struct i915_address_space *vm) return container_of(vm, struct i915_ggtt, base); } +#define INTEL_MAX_PPAT_ENTRIES 8 + +struct intel_ppat; + +struct intel_ppat_entry { + struct intel_ppat *ppat; + struct kref ref_count; + u8 value; +}; + +struct intel_ppat { + struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; + DECLARE_BITMAP(reserved, INTEL_MAX_PPAT_ENTRIES); + DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); + + unsigned int max_entries; + + u8 dummy_value; + /* + * Return a score to show how two PPAT values match, + * a ~0 indicates a perfect match + */ + unsigned int (*match)(u8 src, u8 dst); + /* + * Write the PPAT configuration into HW. + */ + void (*update)(struct drm_i915_private *dev_priv); + + struct drm_i915_private *dev_priv; +}; + +void intel_ppat_reserve(struct intel_ppat *ppat, unsigned int index, u8 value); +struct intel_ppat_entry *intel_ppat_get(struct drm_i915_private *i915, + u8 value); +void intel_ppat_put(struct intel_ppat_entry *entry); + int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);