From patchwork Thu Aug 31 19:36:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9932737 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 50B146022E for ; Thu, 31 Aug 2017 19:36:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 42821288C2 for ; Thu, 31 Aug 2017 19:36:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 37735288FC; Thu, 31 Aug 2017 19:36:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7244288C2 for ; Thu, 31 Aug 2017 19:36:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F25E6E76F; Thu, 31 Aug 2017 19:36:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 489AC6E76E; Thu, 31 Aug 2017 19:36:40 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Aug 2017 12:36:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.41,454,1498546800"; d="scan'208"; a="1168031328" Received: from dmakoshe-mobl.ger.corp.intel.com (HELO zhiwang1-MOBL.ger.corp.intel.com) ([10.252.11.97]) by orsmga001.jf.intel.com with ESMTP; 31 Aug 2017 12:36:37 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Fri, 1 Sep 2017 03:36:17 +0800 Message-Id: <1504208177-27784-4-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504208177-27784-1-git-send-email-zhi.a.wang@intel.com> References: <1504208177-27784-1-git-send-email-zhi.a.wang@intel.com> Cc: Rodrigo Vivi , Ben Widawsky Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Do not allocate unused PPAT entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation during initialization. Cc: Ben Widawsky Cc: Rodrigo Vivi Cc: Chris Wilson Suggested-by: Joonas Lahtinen Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 46 ++++++++++++++++--------------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++++++ 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 51bb382..57f719d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2988,18 +2988,15 @@ static void cnl_setup_private_ppat(struct intel_ppat *ppat) /* XXX: spec is unclear if this is still needed for CNL+ */ if (!USES_PPGTT(ppat->i915)) { - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC); return; } - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); - __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); - __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); - __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); - __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); - __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); - __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); - __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); } /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability @@ -3026,18 +3023,18 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat) * So we can still hold onto all our assumptions wrt cpu * clflushing on LLC machines. */ - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC); return; } - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */ - __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */ - __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */ - __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */ - __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); - __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); - __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); - __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + /* for normal objects, no eLLC */ + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLC); + /* for scanout with eLLC */ + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + /* Uncached objects, mostly for scanout */ + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); } static void chv_setup_private_ppat(struct intel_ppat *ppat) @@ -3066,14 +3063,11 @@ static void chv_setup_private_ppat(struct intel_ppat *ppat) * in order to keep the global status page working. */ - __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 1, 0); - __alloc_ppat_entry(ppat, 2, 0); - __alloc_ppat_entry(ppat, 3, 0); - __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), CHV_PPAT_SNOOP); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), 0); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), 0); + __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), CHV_PPAT_SNOOP); } static void gen6_gmch_remove(struct i915_address_space *vm) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index e10ca89..575da15 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -131,6 +131,13 @@ typedef u64 gen8_ppgtt_pml4e_t; #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ +/* PPAT index = 4 * PAT + 2 * PCD + PWT */ +static inline unsigned int ppat_bits_to_index(unsigned int bits) +{ + return (4 * !!(bits & _PAGE_PAT) + 2 * !!(bits & _PAGE_PCD) + + !!(bits & _PAGE_PWT)); +} + #define CHV_PPAT_SNOOP (1<<6) #define GEN8_PPAT_AGE(x) (x<<4) #define GEN8_PPAT_LLCeLLC (3<<2)