From patchwork Fri Sep 1 07:25:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9933651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 90E6F6016C for ; Fri, 1 Sep 2017 07:22:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8200A2855D for ; Fri, 1 Sep 2017 07:22:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 76E172857D; Fri, 1 Sep 2017 07:22:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 068542855D for ; Fri, 1 Sep 2017 07:22:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06A816E7FF; Fri, 1 Sep 2017 07:22:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA7DD6E803 for ; Fri, 1 Sep 2017 07:22:26 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 01 Sep 2017 00:22:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,457,1498546800"; d="scan'208";a="144393460" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2017 00:22:25 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Sep 2017 12:55:19 +0530 Message-Id: <1504250723-32018-17-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504250723-32018-1-git-send-email-sagar.a.kamble@intel.com> References: <1504250723-32018-1-git-send-email-sagar.a.kamble@intel.com> Cc: Tom O'Rourke Subject: [Intel-gfx] [PATCH 16/20] drm/i915/slpc: Add i915_slpc_info to debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke i915_slpc_info shows the contents of SLPC shared data parsed into text format. v1: Reformat slpc info (Radek) squashed query task state info in slpc info, kunmap before seq_print (Paulo) return void instead of ignored return value (Paulo) Avoid magic numbers and use local variables (Jon Bloomfield) Removed WARN_ON for checking msb of gtt address of shared gem obj. (ChrisW) Moved definition of power plan and power source to earlier patch in the series. drm/i915/slpc: Allocate/Release/Initialize SLPC shared data (Akash) v2-v3: Rebase. v4: Updated with GuC firmware v9. v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event structure. Removed unnecessary checks of vma from i915_slpc_info. Created helpers for reading the SLPC shared data and string form of SLPC state. (Sagar) Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 165 ++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8d0d094..8439ec2 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1022,6 +1022,170 @@ static int i915_error_state_open(struct inode *inode, struct file *file) NULL, i915_next_seqno_set, "0x%llx\n"); +static int i915_slpc_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + int i, value; + struct slpc_shared_data data; + enum slpc_global_state global_state; + enum slpc_platform_sku platform_sku; + struct slpc_task_state_data *task_data; + enum slpc_power_plan power_plan; + enum slpc_power_source power_source; + + if (!dev_priv->guc.slpc.active) + return -ENODEV; + + intel_runtime_pm_get(dev_priv); + mutex_lock(&dev_priv->rps.hw_lock); + + intel_slpc_read_shared_data(&dev_priv->guc.slpc, &data); + + mutex_unlock(&dev_priv->rps.hw_lock); + intel_runtime_pm_put(dev_priv); + + seq_printf(m, "shared data size: %d\n", data.shared_data_size); + + global_state = (enum slpc_global_state) data.global_state; + seq_printf(m, "global state: %d (", global_state); + seq_printf(m, "%s)\n", intel_slpc_get_state_str(global_state)); + + platform_sku = (enum slpc_platform_sku) + data.platform_info.platform_sku; + seq_printf(m, "sku: %d (", platform_sku); + switch (platform_sku) { + case SLPC_PLATFORM_SKU_UNDEFINED: + seq_puts(m, "undefined)\n"); + break; + case SLPC_PLATFORM_SKU_ULX: + seq_puts(m, "ULX)\n"); + break; + case SLPC_PLATFORM_SKU_ULT: + seq_puts(m, "ULT)\n"); + break; + case SLPC_PLATFORM_SKU_T: + seq_puts(m, "T)\n"); + break; + case SLPC_PLATFORM_SKU_MOBL: + seq_puts(m, "Mobile)\n"); + break; + case SLPC_PLATFORM_SKU_DT: + seq_puts(m, "DT)\n"); + break; + case SLPC_PLATFORM_SKU_UNKNOWN: + default: + seq_puts(m, "unknown)\n"); + break; + } + seq_printf(m, "slice count: %d\n", + data.platform_info.slice_count); + + seq_printf(m, "power plan/source: 0x%x\n\tplan:\t", + data.platform_info.power_plan_source); + power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN( + data.platform_info.power_plan_source); + power_source = (enum slpc_power_source) SLPC_POWER_SOURCE( + data.platform_info.power_plan_source); + switch (power_plan) { + case SLPC_POWER_PLAN_UNDEFINED: + seq_puts(m, "undefined"); + break; + case SLPC_POWER_PLAN_BATTERY_SAVER: + seq_puts(m, "battery saver"); + break; + case SLPC_POWER_PLAN_BALANCED: + seq_puts(m, "balanced"); + break; + case SLPC_POWER_PLAN_PERFORMANCE: + seq_puts(m, "performance"); + break; + case SLPC_POWER_PLAN_UNKNOWN: + default: + seq_puts(m, "unknown"); + break; + } + seq_puts(m, "\n\tsource:\t"); + switch (power_source) { + case SLPC_POWER_SOURCE_UNDEFINED: + seq_puts(m, "undefined\n"); + break; + case SLPC_POWER_SOURCE_AC: + seq_puts(m, "AC\n"); + break; + case SLPC_POWER_SOURCE_DC: + seq_puts(m, "DC\n"); + break; + case SLPC_POWER_SOURCE_UNKNOWN: + default: + seq_puts(m, "unknown\n"); + break; + } + + seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n", + data.platform_info.P0_freq * 50, + data.platform_info.P1_freq * 50, + data.platform_info.Pe_freq * 50, + data.platform_info.Pn_freq * 50); + + task_data = &data.task_state_data; + seq_printf(m, "task state data: 0x%08x 0x%08x\n", + task_data->bitfield1, task_data->bitfield2); + + seq_printf(m, "\tgtperf task active: %s\n", + yesno(task_data->gtperf_task_active)); + seq_printf(m, "\tgtperf stall possible: %s\n", + yesno(task_data->gtperf_stall_possible)); + seq_printf(m, "\tgtperf gaming mode: %s\n", + yesno(task_data->gtperf_gaming_mode)); + seq_printf(m, "\tgtperf target fps: %d\n", + task_data->gtperf_target_fps); + + seq_printf(m, "\tdcc task active: %s\n", + yesno(task_data->dcc_task_active)); + seq_printf(m, "\tin dcc: %s\n", + yesno(task_data->in_dcc)); + seq_printf(m, "\tin dct: %s\n", + yesno(task_data->in_dct)); + seq_printf(m, "\tfreq switch active: %s\n", + yesno(task_data->freq_switch_active)); + + seq_printf(m, "\tibc enabled: %s\n", + yesno(task_data->ibc_enabled)); + seq_printf(m, "\tibc active: %s\n", + yesno(task_data->ibc_active)); + seq_printf(m, "\tpg1 enabled: %s\n", + yesno(task_data->pg1_enabled)); + seq_printf(m, "\tpg1 active: %s\n", + yesno(task_data->pg1_active)); + + seq_printf(m, "\tunslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_unslice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tunslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_unslice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_slice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_slice_freq * GEN9_FREQ_SCALER)); + + seq_puts(m, "override parameter bitfield\n"); + for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++) + seq_printf(m, "%d: 0x%08x\n", i, + data.override_parameters_set_bits[i]); + + seq_puts(m, "override parameters (only non-zero shown)\n"); + for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) { + value = data.override_parameters_values[i]; + if (value) + seq_printf(m, "%d: 0x%8x\n", i, value); + } + + return 0; +} + static int i915_frequency_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4851,6 +5015,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, {"i915_huc_load_status", i915_huc_load_status_info, 0}, {"i915_slpc_paramlist", i915_slpc_paramlist_info, 0}, + {"i915_slpc_info", i915_slpc_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, {"i915_reset_info", i915_reset_info, 0},