diff mbox

[06/20] drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers

Message ID 1504250723-32018-7-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com Sept. 1, 2017, 7:25 a.m. UTC 
SLPC operates based on parameters setup in shared data between
i915 and GuC SLPC. This is to be created/initialized in intel_slpc_init.
>From then onwards i915 can control the SLPC operations by Enabling,
Disabling complete SLPC or changing SLPC parameters. During cleanup
SLPC shared data has to be freed.
With this patch on platforms with SLPC support we call intel_slpc_*()
functions from GuC setup functions and do not use Host rps functions.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. In the later patch intel_init_gt_powersave will check
if SLPC has started running through shared data and update initial
state that i915 needs like frequency limits.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
    that are based on SLPC active status in GuC. State setup/cleanup needed
    for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
    init and enabling to GuC enable path as SLPC in GuC can start doing the
    setup post GuC init. Commit message update. (Sagar)

v6: Rearranged function definitions.

v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
    mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
    update.

v8: Changed parameters for SLPC functions to struct intel_slpc*.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  1 +
 drivers/gpu/drm/i915/i915_drv.h   | 12 +++++++++++
 drivers/gpu/drm/i915/i915_irq.c   |  5 +++++
 drivers/gpu/drm/i915/intel_guc.c  |  5 +++++
 drivers/gpu/drm/i915/intel_guc.h  |  3 +++
 drivers/gpu/drm/i915/intel_pm.c   | 23 ++++++++++++++++++---
 drivers/gpu/drm/i915/intel_slpc.c | 42 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 37 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c   | 25 +++++++++++++++++++++++
 9 files changed, 150 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index efc5b30..98b4a9a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -64,6 +64,7 @@  i915-y += intel_uc.o \
 	  intel_guc_log.o \
 	  intel_guc_loader.o \
 	  intel_huc.o \
+	  intel_slpc.o \
 	  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5822d1f..64ba847 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2710,6 +2710,18 @@  static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
 	return container_of(guc, struct drm_i915_private, guc);
 }
 
+static inline struct intel_guc *slpc_to_guc(struct intel_slpc *slpc)
+{
+	return container_of(slpc, struct intel_guc, slpc);
+}
+
+static inline struct drm_i915_private *slpc_to_i915(struct intel_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+
+	return guc_to_i915(guc);
+}
+
 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
 {
 	return container_of(huc, struct drm_i915_private, huc);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..0ff070f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2620,6 +2620,11 @@  static void i915_reset_device(struct drm_i915_private *dev_priv)
 		set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
 		wake_up_all(&dev_priv->gpu_error.wait_queue);
 
+		/*
+		 * TODO: Enable SLPC with TDR indication to SLPC in case of
+		 * Engine Reset.
+		 */
+
 		/* Wait for anyone holding the lock to wakeup, without
 		 * blocking indefinitely on struct_mutex.
 		 */
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index da81c37..a9e7cb0 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -349,6 +349,11 @@  void intel_guc_fini(struct intel_guc *guc)
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_device *dev = &dev_priv->drm;
 
+	if (i915.enable_slpc) {
+		if (dev_priv->guc.slpc.active)
+			intel_slpc_disable(&dev_priv->guc.slpc);
+	}
+
 	if (i915.enable_guc_submission) {
 		mutex_lock(&dev->struct_mutex);
 		i915_guc_submission_disable(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index e77ce1f..dd94f92 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -29,6 +29,7 @@ 
 #include "intel_ringbuffer.h"
 #include "intel_guc_ct.h"
 #include "i915_vma.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
@@ -136,6 +137,8 @@  struct intel_guc {
 		enum forcewake_domains fw_domains;
 	} send_regs;
 
+	struct intel_slpc slpc;
+
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a1b32e1..2452e2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6117,6 +6117,9 @@  static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
+	if (!dev_priv->rps.rps_enabled)
+		return;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.rps_enabled) {
 		u8 freq;
@@ -6145,6 +6148,9 @@  void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	if (!dev_priv->rps.rps_enabled)
+		return;
+
 	/* Flush our bottom-half so that it does not race with us
 	 * setting the idle frequency and so that it is bounded by
 	 * our rpm wakeref. And then disable the interrupts to stop any
@@ -7808,6 +7814,12 @@  void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_put(dev_priv);
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
+
+	if (dev_priv->guc.slpc.active) {
+		intel_runtime_pm_get(dev_priv);
+		intel_slpc_disable(&dev_priv->guc.slpc);
+		intel_runtime_pm_put(dev_priv);
+	}
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7908,15 +7920,20 @@  void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
 	}
-	__intel_enable_gt_powersave(dev_priv);
+
+	if (!i915.enable_slpc)
+		__intel_enable_gt_powersave(dev_priv);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
 #define GT_POWERSAVE_ENABLED(dev_priv) \
 	(((INTEL_GEN(dev_priv) >= 9) && \
-		(READ_ONCE(dev_priv->rps.rps_enabled) && \
-		 READ_ONCE(dev_priv->rps.rc6_enabled))) || \
+		((!i915.enable_slpc && \
+		  READ_ONCE(dev_priv->rps.rps_enabled) && \
+		  READ_ONCE(dev_priv->rps.rc6_enabled)) || \
+		 (i915.enable_slpc && \
+		  READ_ONCE(dev_priv->rps.rc6_enabled)))) || \
 	 ((INTEL_GEN(dev_priv) < 9) && \
 		READ_ONCE(dev_priv->rps.rps_enabled)))
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..06abda5
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,42 @@ 
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_uc.h"
+
+void intel_slpc_init(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_cleanup(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_enable(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_disable(struct intel_slpc *slpc)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..1a93719
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,37 @@ 
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+struct intel_slpc {
+	bool active;
+};
+
+/* intel_slpc.c */
+void intel_slpc_init(struct intel_slpc *slpc);
+void intel_slpc_cleanup(struct intel_slpc *slpc);
+void intel_slpc_enable(struct intel_slpc *slpc);
+void intel_slpc_disable(struct intel_slpc *slpc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 19a2847..bd23d69 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -302,6 +302,9 @@  int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		ret = i915_guc_submission_init(dev_priv);
 		if (ret)
 			goto err_guc;
+
+		if (i915.enable_slpc)
+			intel_slpc_init(&dev_priv->guc.slpc);
 	}
 
 	/* init WOPCM */
@@ -345,6 +348,17 @@  int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		goto err_log_capture;
 
 	intel_huc_auth(huc);
+
+	/*
+	 * SLPC is enabled by setting up the shared data structure and
+	 * sending reset event to GuC SLPC. Initial data is setup in
+	 * intel_slpc_init. Here we send the reset event. SLPC enabling
+	 * in GuC can happen in parallel in GuC with other initialization
+	 * being done in i915.
+	 */
+	if (i915.enable_slpc)
+		intel_slpc_enable(&dev_priv->guc.slpc);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
@@ -374,6 +388,12 @@  int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	if (i915.enable_guc_submission)
 		i915_guc_submission_fini(dev_priv);
 err_guc:
+	if (i915.enable_slpc) {
+		if (dev_priv->guc.slpc.active)
+			intel_slpc_disable(&dev_priv->guc.slpc);
+		intel_slpc_cleanup(&dev_priv->guc.slpc);
+	}
+
 	i915_ggtt_disable_guc(dev_priv);
 
 	DRM_ERROR("GuC init failed\n");
@@ -390,6 +410,8 @@  int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	i915.enable_guc_loading = 0;
 	DRM_NOTE("GuC firmware loading disabled\n");
 
+	i915.enable_slpc = 0;
+
 	return ret;
 }
 
@@ -407,4 +429,7 @@  void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv)
 
 	if (i915.enable_guc_submission)
 		i915_guc_submission_fini(dev_priv);
+
+	if (i915.enable_slpc)
+		intel_slpc_cleanup(&dev_priv->guc.slpc);
 }