From patchwork Fri Sep 1 15:56:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rogozhkin, Dmitry V" X-Patchwork-Id: 9935397 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7F785603B4 for ; Fri, 1 Sep 2017 23:59:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 724152841D for ; Fri, 1 Sep 2017 23:59:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65DC028557; Fri, 1 Sep 2017 23:59:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78F622842B for ; Fri, 1 Sep 2017 23:59:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8E356E8BF; Fri, 1 Sep 2017 23:58:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7499F6E8D3 for ; Fri, 1 Sep 2017 23:58:47 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2017 16:58:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,459,1498546800"; d="scan'208";a="130893843" Received: from dvrscl.jf.intel.com ([10.54.70.8]) by orsmga002.jf.intel.com with ESMTP; 01 Sep 2017 16:58:41 -0700 From: Dmitry Rogozhkin To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Sep 2017 08:56:28 -0700 Message-Id: <1504281392-9095-2-git-send-email-dmitry.v.rogozhkin@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504281392-9095-1-git-send-email-dmitry.v.rogozhkin@intel.com> References: <1504281392-9095-1-git-send-email-dmitry.v.rogozhkin@intel.com> Cc: Peter Zijlstra Subject: [Intel-gfx] [RFC v4 1/5] drm/i915/pmu: reorder function to suite next patch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch is doing nover except reordering functions to highlight changes in the next patch. Change-Id: I0cd298780503ae8f6f8035b86c59fc8b5191356b Signed-off-by: Dmitry Rogozhkin Cc: Tvrtko Ursulin Cc: Peter Zijlstra --- drivers/gpu/drm/i915/i915_pmu.c | 180 ++++++++++++++++++++-------------------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 3272ec0..bcdf2bc 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -363,6 +363,88 @@ static bool engine_needs_busy_stats(struct intel_engine_cs *engine) (engine->pmu.enable & BIT(I915_SAMPLE_BUSY)); } +static u64 count_interrupts(struct drm_i915_private *i915) +{ + /* open-coded kstat_irqs() */ + struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq); + u64 sum = 0; + int cpu; + + if (!desc || !desc->kstat_irqs) + return 0; + + for_each_possible_cpu(cpu) + sum += *per_cpu_ptr(desc->kstat_irqs, cpu); + + return sum; +} + +static void i915_pmu_event_read(struct perf_event *event) +{ + struct drm_i915_private *i915 = + container_of(event->pmu, typeof(*i915), pmu.base); + u64 val = 0; + + if (is_engine_event(event)) { + u8 sample = engine_event_sample(event); + struct intel_engine_cs *engine; + + engine = intel_engine_lookup_user(i915, + engine_event_class(event), + engine_event_instance(event)); + + if (WARN_ON_ONCE(!engine)) { + /* Do nothing */ + } else if (sample == I915_SAMPLE_BUSY && + engine->pmu.busy_stats) { + val = ktime_to_ns(intel_engine_get_busy_time(engine)); + } else { + val = engine->pmu.sample[sample]; + } + } else switch (event->attr.config) { + case I915_PMU_ACTUAL_FREQUENCY: + val = i915->pmu.sample[__I915_SAMPLE_FREQ_ACT]; + break; + case I915_PMU_REQUESTED_FREQUENCY: + val = i915->pmu.sample[__I915_SAMPLE_FREQ_REQ]; + break; + case I915_PMU_ENERGY: + val = intel_energy_uJ(i915); + break; + case I915_PMU_INTERRUPTS: + val = count_interrupts(i915); + break; + + case I915_PMU_RC6_RESIDENCY: + if (!i915->gt.awake) + return; + + val = intel_rc6_residency_ns(i915, + IS_VALLEYVIEW(i915) ? + VLV_GT_RENDER_RC6 : + GEN6_GT_GFX_RC6); + break; + + case I915_PMU_RC6p_RESIDENCY: + if (!i915->gt.awake) + return; + + if (!IS_VALLEYVIEW(i915)) + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); + break; + + case I915_PMU_RC6pp_RESIDENCY: + if (!i915->gt.awake) + return; + + if (!IS_VALLEYVIEW(i915)) + val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); + break; + } + + local64_set(&event->count, val); +} + static void i915_pmu_enable(struct perf_event *event) { struct drm_i915_private *i915 = @@ -440,23 +522,6 @@ static void i915_pmu_disable(struct perf_event *event) i915_pmu_timer_cancel(event); } -static int i915_pmu_event_add(struct perf_event *event, int flags) -{ - struct hw_perf_event *hwc = &event->hw; - - if (flags & PERF_EF_START) - i915_pmu_enable(event); - - hwc->state = !(flags & PERF_EF_START); - - return 0; -} - -static void i915_pmu_event_del(struct perf_event *event, int flags) -{ - i915_pmu_disable(event); -} - static void i915_pmu_event_start(struct perf_event *event, int flags) { i915_pmu_enable(event); @@ -467,86 +532,21 @@ static void i915_pmu_event_stop(struct perf_event *event, int flags) i915_pmu_disable(event); } -static u64 count_interrupts(struct drm_i915_private *i915) +static int i915_pmu_event_add(struct perf_event *event, int flags) { - /* open-coded kstat_irqs() */ - struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq); - u64 sum = 0; - int cpu; + struct hw_perf_event *hwc = &event->hw; - if (!desc || !desc->kstat_irqs) - return 0; + if (flags & PERF_EF_START) + i915_pmu_enable(event); - for_each_possible_cpu(cpu) - sum += *per_cpu_ptr(desc->kstat_irqs, cpu); + hwc->state = !(flags & PERF_EF_START); - return sum; + return 0; } -static void i915_pmu_event_read(struct perf_event *event) +static void i915_pmu_event_del(struct perf_event *event, int flags) { - struct drm_i915_private *i915 = - container_of(event->pmu, typeof(*i915), pmu.base); - u64 val = 0; - - if (is_engine_event(event)) { - u8 sample = engine_event_sample(event); - struct intel_engine_cs *engine; - - engine = intel_engine_lookup_user(i915, - engine_event_class(event), - engine_event_instance(event)); - - if (WARN_ON_ONCE(!engine)) { - /* Do nothing */ - } else if (sample == I915_SAMPLE_BUSY && - engine->pmu.busy_stats) { - val = ktime_to_ns(intel_engine_get_busy_time(engine)); - } else { - val = engine->pmu.sample[sample]; - } - } else switch (event->attr.config) { - case I915_PMU_ACTUAL_FREQUENCY: - val = i915->pmu.sample[__I915_SAMPLE_FREQ_ACT]; - break; - case I915_PMU_REQUESTED_FREQUENCY: - val = i915->pmu.sample[__I915_SAMPLE_FREQ_REQ]; - break; - case I915_PMU_ENERGY: - val = intel_energy_uJ(i915); - break; - case I915_PMU_INTERRUPTS: - val = count_interrupts(i915); - break; - - case I915_PMU_RC6_RESIDENCY: - if (!i915->gt.awake) - return; - - val = intel_rc6_residency_ns(i915, - IS_VALLEYVIEW(i915) ? - VLV_GT_RENDER_RC6 : - GEN6_GT_GFX_RC6); - break; - - case I915_PMU_RC6p_RESIDENCY: - if (!i915->gt.awake) - return; - - if (!IS_VALLEYVIEW(i915)) - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); - break; - - case I915_PMU_RC6pp_RESIDENCY: - if (!i915->gt.awake) - return; - - if (!IS_VALLEYVIEW(i915)) - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); - break; - } - - local64_set(&event->count, val); + i915_pmu_disable(event); } static int i915_pmu_event_event_idx(struct perf_event *event)