From patchwork Fri Sep 8 18:06:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9944815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 70D4F60224 for ; Fri, 8 Sep 2017 18:06:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D34C28844 for ; Fri, 8 Sep 2017 18:06:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 503D428862; Fri, 8 Sep 2017 18:06:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E335F28844 for ; Fri, 8 Sep 2017 18:06:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61B146EBF4; Fri, 8 Sep 2017 18:06:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78BB76EBF2; Fri, 8 Sep 2017 18:06:52 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Sep 2017 11:06:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,362,1500966000"; d="scan'208";a="147099244" Received: from ciaragor-mobl.ger.corp.intel.com (HELO zhiwang1-MOBL.ger.corp.intel.com) ([10.252.5.221]) by orsmga005.jf.intel.com with ESMTP; 08 Sep 2017 11:06:49 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Sat, 9 Sep 2017 02:06:38 +0800 Message-Id: <1504893999-15403-4-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504893999-15403-1-git-send-email-zhi.a.wang@intel.com> References: <1504893999-15403-1-git-send-email-zhi.a.wang@intel.com> Cc: Rodrigo Vivi , Ben Widawsky Subject: [Intel-gfx] [PATCH v9 4/5] drm/i915: Do not allocate unused PPAT entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation during initialization. v8: - Move ppat_index() into i915_gem_gtt.c. (Chris) - Change the name of ppat_bits_to_index to ppat_index. Cc: Ben Widawsky Cc: Rodrigo Vivi Cc: Chris Wilson Suggested-by: Joonas Lahtinen Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 53 +++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index d8d2b4a..82cb97b 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2979,6 +2979,13 @@ static unsigned int chv_private_pat_match(u8 src, u8 dst) INTEL_PPAT_PERFECT_MATCH : 0; } +/* PPAT index = 4 * PAT + 2 * PCD + PWT */ +static inline unsigned int ppat_index(unsigned int bits) +{ + return (4 * !!(bits & _PAGE_PAT) + 2 * !!(bits & _PAGE_PCD) + + !!(bits & _PAGE_PWT)); +} + static void cnl_setup_private_ppat(struct intel_ppat *ppat) { ppat->max_entries = 8; @@ -2988,18 +2995,15 @@ static void cnl_setup_private_ppat(struct intel_ppat *ppat) /* XXX: spec is unclear if this is still needed for CNL+ */ if (!USES_PPGTT(ppat->i915)) { - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_UC); return; } - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); - __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); - __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); - __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); - __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); - __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); - __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); - __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB | GEN8_PPAT_LLC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); } /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability @@ -3026,18 +3030,18 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat) * So we can still hold onto all our assumptions wrt cpu * clflushing on LLC machines. */ - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_UC); return; } - __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */ - __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */ - __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */ - __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */ - __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); - __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); - __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); - __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + /* for normal objects, no eLLC */ + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB | GEN8_PPAT_LLC); + /* for scanout with eLLC */ + __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + /* Uncached objects, mostly for scanout */ + __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC); + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); } static void chv_setup_private_ppat(struct intel_ppat *ppat) @@ -3066,14 +3070,11 @@ static void chv_setup_private_ppat(struct intel_ppat *ppat) * in order to keep the global status page working. */ - __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 1, 0); - __alloc_ppat_entry(ppat, 2, 0); - __alloc_ppat_entry(ppat, 3, 0); - __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP); - __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP); + /* See gen8_pte_encode() for the mapping from cache-level to PPAT */ + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), CHV_PPAT_SNOOP); + __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), 0); + __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), 0); + __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), CHV_PPAT_SNOOP); } static void gen6_gmch_remove(struct i915_address_space *vm)