| Message ID | 1505207980-18439-2-git-send-email-juhapekka.heikkila@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Sep 12, 2017 at 12:19:38PM +0300, Juha-Pekka Heikkila wrote: > Move u32 dspaddr_offset from struct intel_crtc member into local > variable in i9xx_update_primary_plane() You fail to update the skl function, so this won't build. Please make sure each step in the series builds (and ideally also works). That way people can actually bisect through the series. > > Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > --- > drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- > drivers/gpu/drm/i915/intel_drv.h | 1 - > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 0871807..0dd0e2a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3307,13 +3307,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, > int x = plane_state->main.x; > int y = plane_state->main.y; > unsigned long irqflags; > + u32 dspaddr_offset; > > linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); > > if (INTEL_GEN(dev_priv) >= 4) > - crtc->dspaddr_offset = plane_state->main.offset; > + dspaddr_offset = plane_state->main.offset; > else > - crtc->dspaddr_offset = linear_offset; > + dspaddr_offset = linear_offset; > > crtc->adjusted_x = x; > crtc->adjusted_y = y; > @@ -3342,18 +3343,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > I915_WRITE_FW(DSPSURF(plane), > intel_plane_ggtt_offset(plane_state) + > - crtc->dspaddr_offset); > + dspaddr_offset); > I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); > } else if (INTEL_GEN(dev_priv) >= 4) { > I915_WRITE_FW(DSPSURF(plane), > intel_plane_ggtt_offset(plane_state) + > - crtc->dspaddr_offset); > + dspaddr_offset); > I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); > I915_WRITE_FW(DSPLINOFF(plane), linear_offset); > } else { > I915_WRITE_FW(DSPADDR(plane), > intel_plane_ggtt_offset(plane_state) + > - crtc->dspaddr_offset); > + dspaddr_offset); > } > POSTING_READ_FW(reg); > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 3078076..d58cd10 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -806,7 +806,6 @@ struct intel_crtc { > /* Display surface base address adjustement for pageflips. Note that on > * gen4+ this only adjusts up to a tile, offsets within a tile are > * handled in the hw itself (with the TILEOFF register). */ > - u32 dspaddr_offset; > int adjusted_x; > int adjusted_y; > > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0871807..0dd0e2a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3307,13 +3307,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, int x = plane_state->main.x; int y = plane_state->main.y; unsigned long irqflags; + u32 dspaddr_offset; linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); if (INTEL_GEN(dev_priv) >= 4) - crtc->dspaddr_offset = plane_state->main.offset; + dspaddr_offset = plane_state->main.offset; else - crtc->dspaddr_offset = linear_offset; + dspaddr_offset = linear_offset; crtc->adjusted_x = x; crtc->adjusted_y = y; @@ -3342,18 +3343,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { I915_WRITE_FW(DSPSURF(plane), intel_plane_ggtt_offset(plane_state) + - crtc->dspaddr_offset); + dspaddr_offset); I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { I915_WRITE_FW(DSPSURF(plane), intel_plane_ggtt_offset(plane_state) + - crtc->dspaddr_offset); + dspaddr_offset); I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); I915_WRITE_FW(DSPLINOFF(plane), linear_offset); } else { I915_WRITE_FW(DSPADDR(plane), intel_plane_ggtt_offset(plane_state) + - crtc->dspaddr_offset); + dspaddr_offset); } POSTING_READ_FW(reg); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3078076..d58cd10 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -806,7 +806,6 @@ struct intel_crtc { /* Display surface base address adjustement for pageflips. Note that on * gen4+ this only adjusts up to a tile, offsets within a tile are * handled in the hw itself (with the TILEOFF register). */ - u32 dspaddr_offset; int adjusted_x; int adjusted_y;
Move u32 dspaddr_offset from struct intel_crtc member into local variable in i9xx_update_primary_plane() Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- drivers/gpu/drm/i915/intel_drv.h | 1 - 2 files changed, 6 insertions(+), 6 deletions(-)