diff mbox

drm/i915/cnl: Add Gen10 LRC size

Message ID 1506035989-14295-1-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com Sept. 21, 2017, 11:19 p.m. UTC
The total size of the context has decreased with the removal of the
URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
one page for PPHWSP, and I'm throwing an extra page for precaution.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Rodrigo Vivi Sept. 22, 2017, 1:29 p.m. UTC | #1
On Thu, Sep 21, 2017 at 11:19:49PM +0000, Oscar Mateo wrote:
> The total size of the context has decreased with the removal of the
> URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> one page for PPHWSP, and I'm throwing an extra page for precaution.

I could never find this info on bspec... could you please point that to
me?

Anyways this value matches with other HW engineers had told me a while
ago, and we now have CNL on CI, so:

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 3d135c3..a3115f3 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -39,6 +39,7 @@
>  
>  #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
>  #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
> +#define GEN10_LR_CONTEXT_RENDER_SIZE	(19 * PAGE_SIZE)
>  
>  #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
>  
> @@ -150,6 +151,7 @@ struct engine_info {
>  		default:
>  			MISSING_CASE(INTEL_GEN(dev_priv));
>  		case 10:
> +			return GEN10_LR_CONTEXT_RENDER_SIZE;
>  		case 9:
>  			return GEN9_LR_CONTEXT_RENDER_SIZE;
>  		case 8:
> -- 
> 1.9.1
>
Rodrigo Vivi Sept. 22, 2017, 2:21 p.m. UTC | #2
On Fri, Sep 22, 2017 at 6:31 AM Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:

> On Thu, Sep 21, 2017 at 11:19:49PM +0000, Oscar Mateo wrote:
> > The total size of the context has decreased with the removal of the
> > URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> > one page for PPHWSP, and I'm throwing an extra page for precaution.
>
> I could never find this info on bspec... could you please point that to
> me?


Michal already pointed the doc to me!
Now I know where that comes from! :)

Patch Merges to dinq.
Thanks


>
> Anyways this value matches with other HW engineers had told me a while
> ago, and we now have CNL on CI, so:
>
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> >
> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Ben Widawsky <ben@bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 3d135c3..a3115f3 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -39,6 +39,7 @@
> >
> >  #define GEN8_LR_CONTEXT_RENDER_SIZE  (20 * PAGE_SIZE)
> >  #define GEN9_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
> > +#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * PAGE_SIZE)
> >
> >  #define GEN8_LR_CONTEXT_OTHER_SIZE   ( 2 * PAGE_SIZE)
> >
> > @@ -150,6 +151,7 @@ struct engine_info {
> >               default:
> >                       MISSING_CASE(INTEL_GEN(dev_priv));
> >               case 10:
> > +                     return GEN10_LR_CONTEXT_RENDER_SIZE;
> >               case 9:
> >                       return GEN9_LR_CONTEXT_RENDER_SIZE;
> >               case 8:
> > --
> > 1.9.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
Joonas Lahtinen Sept. 29, 2017, 10:24 a.m. UTC | #3
On Thu, 2017-09-21 at 16:19 -0700, Oscar Mateo wrote:
> The total size of the context has decreased with the removal of the
> URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> one page for PPHWSP, and I'm throwing an extra page for precaution.

Rather no precaution, or make it for all gens and add a comment.

It's otherwise super confusing to double-check the correctness, been
there, done that :)

Regards, Joonas
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 3d135c3..a3115f3 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -39,6 +39,7 @@ 
 
 #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
 #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
+#define GEN10_LR_CONTEXT_RENDER_SIZE	(19 * PAGE_SIZE)
 
 #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
 
@@ -150,6 +151,7 @@  struct engine_info {
 		default:
 			MISSING_CASE(INTEL_GEN(dev_priv));
 		case 10:
+			return GEN10_LR_CONTEXT_RENDER_SIZE;
 		case 9:
 			return GEN9_LR_CONTEXT_RENDER_SIZE;
 		case 8: