From patchwork Thu Sep 28 03:05:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9975221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 635B86037F for ; Thu, 28 Sep 2017 03:02:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 59A6E2930A for ; Thu, 28 Sep 2017 03:02:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4ECF029334; Thu, 28 Sep 2017 03:02:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D44AB2930A for ; Thu, 28 Sep 2017 03:02:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E7A189E3B; Thu, 28 Sep 2017 03:02:30 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A586898D9 for ; Thu, 28 Sep 2017 03:02:24 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 27 Sep 2017 20:02:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,448,1500966000"; d="scan'208";a="156391183" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga005.fm.intel.com with ESMTP; 27 Sep 2017 20:02:22 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Sep 2017 08:35:32 +0530 Message-Id: <1506567938-3944-6-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506567938-3944-1-git-send-email-sagar.a.kamble@intel.com> References: <1506567938-3944-1-git-send-email-sagar.a.kamble@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v11 05/11] drm/i915/guc: Introduce intel_uc_sanitize X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Currently GPU is reset at the end of suspend via i915_gem_sanitize. On resume, GuC will not be loaded until intel_uc_init_hw happens during GEM resume flow but action to exit sleep can be sent to GuC considering the FW load status. To make sure we don't invoke that action update GuC FW load status at the end of GPU reset as NONE. load_status indicates HW state and it is sanitized through this new function intel_uc_sanitize. v2: Rebase. v3: Removed intel_guc_sanitize. Marking load status as NONE at the GPU reset point. (Chris/Michal) v4: Reinstated the uC function intel_uc_sanitize. (Michal Wajdeczko) Signed-off-by: Sagar Arun Kamble Cc: Michal Wajdeczko Cc: Michał Winiarski Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_uc.c | 12 ++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 3 +++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 80251ec..ab26232 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -508,6 +508,18 @@ int intel_uc_resume(struct drm_i915_private *dev_priv) return intel_guc_resume(dev_priv); } +void intel_uc_sanitize(struct drm_i915_private *dev_priv) +{ + /* + * FIXME: intel_uc_resume currently depends on load_status to resume + * GuC. Since we are resetting Full GPU at the end of suspend, let us + * mark the load status as NONE. Once intel_uc_resume is updated to take + * into consideration GuC load state based on WOPCM, we can skip this + * state update. + */ + dev_priv->guc.fw.load_status = INTEL_UC_FIRMWARE_NONE; +} + int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len) { WARN(1, "Unexpected send: action=%#x\n", *action); diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 0a79e17..ce3cea5 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -212,6 +212,7 @@ struct intel_huc { int intel_uc_runtime_resume(struct drm_i915_private *dev_priv); int intel_uc_suspend(struct drm_i915_private *dev_priv); int intel_uc_resume(struct drm_i915_private *dev_priv); +void intel_uc_sanitize(struct drm_i915_private *dev_priv); int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index b3c3f94..acab013 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1763,6 +1763,9 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) } intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + if (engine_mask == ALL_ENGINES) + intel_uc_sanitize(dev_priv); + return ret; }