From patchwork Sat Oct 7 07:07:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9991219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CE6A360244 for ; Sat, 7 Oct 2017 07:04:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C133121327 for ; Sat, 7 Oct 2017 07:04:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B652026E75; Sat, 7 Oct 2017 07:04:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 20C5921327 for ; Sat, 7 Oct 2017 07:04:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 112526EA4C; Sat, 7 Oct 2017 07:04:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 029F56EA4B for ; Sat, 7 Oct 2017 07:04:33 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2017 00:04:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,487,1500966000"; d="scan'208"; a="1203240963" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga001.fm.intel.com with ESMTP; 07 Oct 2017 00:04:32 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Oct 2017 12:37:35 +0530 Message-Id: <1507360055-19948-13-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507360055-19948-1-git-send-email-sagar.a.kamble@intel.com> References: <1507360055-19948-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v3 12/12] drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Defined new struct intel_rc6 to hold RC6 specific state and intel_ring_pstate to hold ring specific state. v2: s/intel_ring_pstate/intel_llc_pstate. Removed checks from autoenable_* functions. (Chris) Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 10 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 54 ++++++++++++++++++++++++----------------- 3 files changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f3ac1f4..f1e6517 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2502,7 +2502,7 @@ static int intel_runtime_suspend(struct device *kdev) struct drm_i915_private *dev_priv = to_i915(dev); int ret; - if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_rc6_enabled()))) + if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled()))) return -ENODEV; if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d2db2f6..f27e42b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1363,8 +1363,18 @@ struct intel_rps { struct intel_rps_ei ei; }; +struct intel_rc6 { + bool enabled; +}; + +struct intel_llc_pstate { + bool enabled; +}; + struct intel_gen6_power_mgmt { struct intel_rps rps; + struct intel_rc6 rc6; + struct intel_llc_pstate llc_pstate; struct delayed_work autoenable_work; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f125d5f..093861c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7962,7 +7962,8 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) { - dev_priv->gt_pm.rps.enabled = true; /* force disabling */ + dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ + dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); gen6_reset_rps_interrupts(dev_priv); @@ -7972,13 +7973,21 @@ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) { lockdep_assert_held(&i915->pcu_lock); + if (!i915->gt_pm.llc_pstate.enabled) + return; + /* Currently there is no HW configuration to be done to disable. */ + + i915->gt_pm.llc_pstate.enabled = false; } static void intel_disable_rc6(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->pcu_lock); + if (!dev_priv->gt_pm.rc6.enabled) + return; + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rc6(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) @@ -7987,12 +7996,17 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv) valleyview_disable_rc6(dev_priv); else if (INTEL_GEN(dev_priv) >= 6) gen6_disable_rc6(dev_priv); + + dev_priv->gt_pm.rc6.enabled = false; } static void intel_disable_rps(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->pcu_lock); + if (!dev_priv->gt_pm.rps.enabled) + return; + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rps(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) @@ -8003,15 +8017,12 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv) gen6_disable_rps(dev_priv); else if (IS_IRONLAKE_M(dev_priv)) ironlake_disable_drps(dev_priv); + + dev_priv->gt_pm.rps.enabled = false; } void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) { - struct intel_rps *rps = &dev_priv->gt_pm.rps; - - if (!READ_ONCE(rps->enabled)) - return; - mutex_lock(&dev_priv->pcu_lock); intel_disable_rc6(dev_priv); @@ -8019,7 +8030,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) if (HAS_LLC(dev_priv)) intel_disable_llc_pstate(dev_priv); - rps->enabled = false; mutex_unlock(&dev_priv->pcu_lock); } @@ -8027,13 +8037,21 @@ static inline void intel_enable_llc_pstate(struct drm_i915_private *i915) { lockdep_assert_held(&i915->pcu_lock); + if (i915->gt_pm.llc_pstate.enabled) + return; + gen6_update_ring_freq(i915); + + i915->gt_pm.llc_pstate.enabled = true; } static void intel_enable_rc6(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->pcu_lock); + if (dev_priv->gt_pm.rc6.enabled) + return; + if (IS_CHERRYVIEW(dev_priv)) cherryview_enable_rc6(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) @@ -8044,6 +8062,8 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv) gen8_enable_rc6(dev_priv); else if (INTEL_GEN(dev_priv) >= 6) gen6_enable_rc6(dev_priv); + + dev_priv->gt_pm.rc6.enabled = true; } static void intel_enable_rps(struct drm_i915_private *dev_priv) @@ -8052,6 +8072,9 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) lockdep_assert_held(&dev_priv->pcu_lock); + if (rps->enabled) + return; + if (IS_CHERRYVIEW(dev_priv)) { cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { @@ -8072,18 +8095,12 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) WARN_ON(rps->efficient_freq < rps->min_freq); WARN_ON(rps->efficient_freq > rps->max_freq); + + rps->enabled = true; } void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) { - struct intel_rps *rps = &dev_priv->gt_pm.rps; - - /* We shouldn't be disabling as we submit, so this should be less - * racy than it appears! - */ - if (READ_ONCE(rps->enabled)) - return; - /* Powersaving is controlled by the host when inside a VM */ if (intel_vgpu_active(dev_priv)) return; @@ -8095,7 +8112,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) if (HAS_LLC(dev_priv)) intel_enable_llc_pstate(dev_priv); - rps->enabled = true; mutex_unlock(&dev_priv->pcu_lock); } @@ -8108,9 +8124,6 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work) struct intel_engine_cs *rcs; struct drm_i915_gem_request *req; - if (READ_ONCE(dev_priv->gt_pm.rps.enabled)) - goto out; - rcs = dev_priv->engine[RCS]; if (rcs->last_retired_context) goto out; @@ -8138,9 +8151,6 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work) void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) { - if (READ_ONCE(dev_priv->gt_pm.rps.enabled)) - return; - if (IS_IRONLAKE_M(dev_priv)) { ironlake_enable_drps(dev_priv); intel_init_emon(dev_priv);