From patchwork Mon Oct 9 20:58:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 9994317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9880560223 for ; Mon, 9 Oct 2017 20:58:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B7FD28836 for ; Mon, 9 Oct 2017 20:58:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 809732883D; Mon, 9 Oct 2017 20:58:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EE6F028836 for ; Mon, 9 Oct 2017 20:58:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F37E96E3E3; Mon, 9 Oct 2017 20:58:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9F1E06E39B for ; Mon, 9 Oct 2017 20:58:26 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2017 13:58:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,501,1500966000"; d="scan'208";a="161178682" Received: from omateolo-linux.fm.intel.com ([10.1.27.26]) by fmsmga006.fm.intel.com with ESMTP; 09 Oct 2017 13:58:25 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2017 13:58:22 -0700 Message-Id: <1507582707-20079-8-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507582707-20079-1-git-send-email-oscar.mateo@intel.com> References: <1507582707-20079-1-git-send-email-oscar.mateo@intel.com> Subject: [Intel-gfx] [RFC PATCH 07/11] drm/i915: Save all Whitelist WAs and apply them at a later time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Same as we have been doing for other types, this allow us to dump the whole list of workarounds to debugs, for validation purposes. Signed-off-by: Oscar Mateo Cc: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_workarounds.c | 113 ++++++++++++++++---------------- drivers/gpu/drm/i915/i915_workarounds.h | 3 +- drivers/gpu/drm/i915/intel_lrc.c | 8 ++- 5 files changed, 67 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a204896..bfb0648 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3560,7 +3560,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused) seq_printf(m, "Context workarounds applied: %d\n", workarounds->ctx_wa_count); for_each_engine(engine, dev_priv, id) seq_printf(m, "HW whitelist count for %s: %d\n", - engine->name, workarounds->hw_whitelist_count[id]); + engine->name, workarounds->whitelist_wa_count[id]); for (i = 0; i < workarounds->ctx_wa_count; ++i) { i915_reg_t addr; u32 mask, value, read; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b042078..9359231 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1964,7 +1964,8 @@ struct i915_workarounds { struct i915_wa_reg mmio_wa_reg[I915_MAX_MMIO_WA_REGS]; u32 mmio_wa_count; - u32 hw_whitelist_count[I915_NUM_ENGINES]; + struct i915_wa_reg whitelist_wa_reg[I915_NUM_ENGINES][RING_MAX_NONPRIV_SLOTS]; + u32 whitelist_wa_count[I915_NUM_ENGINES]; }; struct i915_virtual_gpu { diff --git a/drivers/gpu/drm/i915/i915_workarounds.c b/drivers/gpu/drm/i915/i915_workarounds.c index 7f9e66a..5f7eb7a 100644 --- a/drivers/gpu/drm/i915/i915_workarounds.c +++ b/drivers/gpu/drm/i915/i915_workarounds.c @@ -869,64 +869,64 @@ void i915_mmio_workarounds_apply(struct drm_i915_private *dev_priv) } } -static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, - i915_reg_t reg) +static int whitelist_wa_add(struct intel_engine_cs *engine, + i915_reg_t reg) { struct drm_i915_private *dev_priv = engine->i915; struct i915_workarounds *wa = &dev_priv->workarounds; - const uint32_t index = wa->hw_whitelist_count[engine->id]; + const uint32_t index = wa->whitelist_wa_count[engine->id]; if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) return -EINVAL; - I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), - i915_mmio_reg_offset(reg)); - wa->hw_whitelist_count[engine->id]++; + wa->whitelist_wa_reg[engine->id][index].addr = + RING_FORCE_TO_NONPRIV(engine->mmio_base, index); + wa->whitelist_wa_reg[engine->id][index].value = i915_mmio_reg_offset(reg); + wa->whitelist_wa_reg[engine->id][index].mask = 0xffffffff; + + wa->whitelist_wa_count[engine->id]++; return 0; } -static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - int ret; +#define WHITELISTWA_REG(engine, reg) do { \ + const int r = whitelist_wa_add(engine, reg); \ + if (r) \ + return r; \ +} while (0) +static int gen9_whitelist_workarounds_init(struct intel_engine_cs *engine) +{ /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ - ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN9_CTX_PREEMPT_REG); /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ - ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN8_CS_CHICKEN1); /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ - ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN8_HDC_CHICKEN1); return 0; } -static int skl_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int skl_whitelist_workarounds_init(struct intel_engine_cs *engine) { - int ret = gen9_whitelist_workarounds_apply(engine); + int ret = gen9_whitelist_workarounds_init(engine); if (ret) return ret; /* WaDisableLSQCROPERFforOCL:skl */ - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN8_L3SQCREG4); return 0; } -static int bxt_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int bxt_whitelist_workarounds_init(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; + int ret; - int ret = gen9_whitelist_workarounds_apply(engine); + ret = gen9_whitelist_workarounds_init(engine); if (ret) return ret; @@ -935,89 +935,90 @@ static int bxt_whitelist_workarounds_apply(struct intel_engine_cs *engine) /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ /* WaDisableLSQCROPERFforOCL:bxt */ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { - ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); - if (ret) - return ret; - - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN9_CS_DEBUG_MODE1); + WHITELISTWA_REG(engine, GEN8_L3SQCREG4); } return 0; } -static int kbl_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int kbl_whitelist_workarounds_init(struct intel_engine_cs *engine) { - int ret = gen9_whitelist_workarounds_apply(engine); + int ret = gen9_whitelist_workarounds_init(engine); if (ret) return ret; /* WaDisableLSQCROPERFforOCL:kbl */ - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN8_L3SQCREG4); return 0; } -static int glk_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int glk_whitelist_workarounds_init(struct intel_engine_cs *engine) { - int ret = gen9_whitelist_workarounds_apply(engine); + int ret = gen9_whitelist_workarounds_init(engine); if (ret) return ret; return 0; } -static int cfl_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int cfl_whitelist_workarounds_init(struct intel_engine_cs *engine) { - int ret = gen9_whitelist_workarounds_apply(engine); + int ret = gen9_whitelist_workarounds_init(engine); if (ret) return ret; return 0; } -static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine) +static int cnl_whitelist_workarounds_init(struct intel_engine_cs *engine) { - int ret; - /* WaEnablePreemptionGranularityControlByUMD:cnl */ - ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); - if (ret) - return ret; + WHITELISTWA_REG(engine, GEN8_CS_CHICKEN1); return 0; } -int i915_whitelist_workarounds_apply(struct intel_engine_cs *engine) +int i915_whitelist_workarounds_init(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; int err; WARN_ON(engine->id != RCS); - dev_priv->workarounds.hw_whitelist_count[engine->id] = 0; + dev_priv->workarounds.whitelist_wa_count[engine->id] = 0; if (IS_SKYLAKE(dev_priv)) - err = skl_whitelist_workarounds_apply(engine); + err = skl_whitelist_workarounds_init(engine); else if (IS_BROXTON(dev_priv)) - err = bxt_whitelist_workarounds_apply(engine); + err = bxt_whitelist_workarounds_init(engine); else if (IS_KABYLAKE(dev_priv)) - err = kbl_whitelist_workarounds_apply(engine); + err = kbl_whitelist_workarounds_init(engine); else if (IS_GEMINILAKE(dev_priv)) - err = glk_whitelist_workarounds_apply(engine); + err = glk_whitelist_workarounds_init(engine); else if (IS_COFFEELAKE(dev_priv)) - err = cfl_whitelist_workarounds_apply(engine); + err = cfl_whitelist_workarounds_init(engine); else if (IS_CANNONLAKE(dev_priv)) - err = cnl_whitelist_workarounds_apply(engine); + err = cnl_whitelist_workarounds_init(engine); else err = 0; if (err) return err; DRM_DEBUG_DRIVER("%s: Number of whitelist w/a: %d\n", engine->name, - dev_priv->workarounds.hw_whitelist_count[engine->id]); + dev_priv->workarounds.whitelist_wa_count[engine->id]); return 0; } + +void i915_whitelist_workarounds_apply(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + struct i915_workarounds *w = &dev_priv->workarounds; + int i; + + for (i = 0; i < w->whitelist_wa_count[engine->id]; i++) { + I915_WRITE(w->whitelist_wa_reg[engine->id][i].addr, + w->whitelist_wa_reg[engine->id][i].value); + } +} diff --git a/drivers/gpu/drm/i915/i915_workarounds.h b/drivers/gpu/drm/i915/i915_workarounds.h index 1ffe13a..805d246 100644 --- a/drivers/gpu/drm/i915/i915_workarounds.h +++ b/drivers/gpu/drm/i915/i915_workarounds.h @@ -31,6 +31,7 @@ int i915_mmio_workarounds_init(struct drm_i915_private *dev_priv); void i915_mmio_workarounds_apply(struct drm_i915_private *dev_priv); -int i915_whitelist_workarounds_apply(struct intel_engine_cs *engine); +int i915_whitelist_workarounds_init(struct intel_engine_cs *engine); +void i915_whitelist_workarounds_apply(struct intel_engine_cs *engine); #endif diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4816dd6..0fe0f3e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1499,9 +1499,7 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine) if (ret) return ret; - ret = i915_whitelist_workarounds_apply(engine); - if (ret) - return ret; + i915_whitelist_workarounds_apply(engine); return 0; } @@ -1988,6 +1986,10 @@ int logical_render_ring_init(struct intel_engine_cs *engine) if (ret) return ret; + ret = i915_whitelist_workarounds_init(engine); + if (ret) + return ret; + ret = intel_init_workaround_bb(engine); if (ret) { /*