From patchwork Fri Oct 13 20:54:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10005949 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5FC0860325 for ; Fri, 13 Oct 2017 20:54:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 50E922901A for ; Fri, 13 Oct 2017 20:54:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45D9F2909F; Fri, 13 Oct 2017 20:54:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E8CA82901A for ; Fri, 13 Oct 2017 20:54:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE0446EC34; Fri, 13 Oct 2017 20:54:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id E81C36EB7D for ; Fri, 13 Oct 2017 20:54:13 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP; 13 Oct 2017 13:54:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.43,372,1503385200"; d="scan'208"; a="1205630089" Received: from omateolo-linux.fm.intel.com ([10.1.27.26]) by fmsmga001.fm.intel.com with ESMTP; 13 Oct 2017 13:54:13 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Fri, 13 Oct 2017 13:54:03 -0700 Message-Id: <1507928056-6966-10-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507928056-6966-1-git-send-email-oscar.mateo@intel.com> References: <1507928056-6966-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 09/22] drm/i915: Print all workaround types correctly in debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Let's try to make sure that all WAs are applied correctly and survive resumes, resets, etc... (with some help from a companion i-g-t patch). v2: - Rebased - Print display WAs as well (Ville) Signed-off-by: Oscar Mateo Cc: Chris Wilson Cc: Mika Kuoppala Cc: Ville Syrjälä --- drivers/gpu/drm/i915/i915_debugfs.c | 53 +++++++++++++++++++++++++++---------- 1 file changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f108f53..11fb9c3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3399,6 +3399,20 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) return 0; } +static void check_wa_register(struct seq_file *m, struct i915_wa_reg *wa_reg) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + u32 read; + bool ok; + + read = I915_READ(wa_reg->addr); + ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask); + seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s\n", + i915_mmio_reg_offset(wa_reg->addr), + wa_reg->value, wa_reg->mask, read, + ok ? "OK" : "FAIL"); +} + static int i915_wa_registers(struct seq_file *m, void *unused) { int i; @@ -3408,6 +3422,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused) struct drm_device *dev = &dev_priv->drm; struct i915_workarounds *workarounds = &dev_priv->workarounds; enum intel_engine_id id; + u32 whitelist_wa_count = 0; ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) @@ -3416,22 +3431,32 @@ static int i915_wa_registers(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); seq_printf(m, "Context workarounds applied: %d\n", workarounds->ctx_wa_count); - for_each_engine(engine, dev_priv, id) - seq_printf(m, "HW whitelist count for %s: %d\n", - engine->name, workarounds->whitelist_wa_count[id]); for (i = 0; i < workarounds->ctx_wa_count; ++i) { - i915_reg_t addr; - u32 mask, value, read; - bool ok; - - addr = workarounds->ctx_wa_reg[i].addr; - mask = workarounds->ctx_wa_reg[i].mask; - value = workarounds->ctx_wa_reg[i].value; - read = I915_READ(addr); - ok = (value & mask) == (read & mask); - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", - i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); + struct i915_wa_reg *wa_reg = &workarounds->ctx_wa_reg[i]; + + seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x\n", + i915_mmio_reg_offset(wa_reg->addr), + wa_reg->value, wa_reg->mask); } + seq_putc(m, '\n'); + + seq_printf(m, "GT workarounds applied: %d\n", workarounds->gt_wa_count); + for (i = 0; i < workarounds->gt_wa_count; ++i) + check_wa_register(m, &workarounds->gt_wa_reg[i]); + seq_putc(m, '\n'); + + seq_printf(m, "Display workarounds applied: %d\n", workarounds->display_wa_count); + for (i = 0; i < workarounds->display_wa_count; ++i) + check_wa_register(m, &workarounds->display_wa_reg[i]); + seq_putc(m, '\n'); + + for_each_engine(engine, dev_priv, id) + whitelist_wa_count += workarounds->whitelist_wa_count[id]; + seq_printf(m, "Whitelist workarounds applied: %d\n", whitelist_wa_count); + for_each_engine(engine, dev_priv, id) + for (i = 0; i < workarounds->whitelist_wa_count[id]; ++i) + check_wa_register(m, &workarounds->whitelist_wa_reg[id][i]); + seq_putc(m, '\n'); intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex);