diff mbox

[v3,12/22] drm/i915/gen9: Move GT and Display workarounds from init_clock_gating

Message ID 1507928056-6966-13-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com Oct. 13, 2017, 8:54 p.m. UTC 
To their rightful place inside intel_workarounds.c

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c          | 51 ------------------------------
 drivers/gpu/drm/i915/intel_workarounds.c | 54 ++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+), 51 deletions(-)

Comments

Chris Wilson Oct. 17, 2017, 12:53 p.m. UTC | #1 
Quoting Oscar Mateo (2017-10-13 21:54:06)
> To their rightful place inside intel_workarounds.c
> 
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3f92bed1..ef74251 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -57,53 +57,8 @@ 
 #define INTEL_RC6p_ENABLE			(1<<1)
 #define INTEL_RC6pp_ENABLE			(1<<2)
 
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-	if (HAS_LLC(dev_priv)) {
-		/*
-		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
-		 * Display WA#0390: skl,kbl
-		 *
-		 * Must match Sampler, Pixel Back End, and Media. See
-		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
-		 */
-		I915_WRITE(CHICKEN_PAR1_1,
-			   I915_READ(CHICKEN_PAR1_1) |
-			   SKL_DE_COMPRESSED_HASH_MODE);
-	}
-
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
-
-	I915_WRITE(GEN8_CONFIG0,
-		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
-
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-	I915_WRITE(GEN8_CHICKEN_DCPR_1,
-		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
-	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
-	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-		   DISP_FBC_WM_DIS |
-		   DISP_FBC_MEMORY_WAKE);
-
-	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-		   ILK_DPFC_DISABLE_DUMMY0);
-
-	if (IS_SKYLAKE(dev_priv)) {
-		/* WaDisableDopClockGating */
-		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
-			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-	}
-}
-
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	gen9_init_clock_gating(dev_priv);
-
 	/* WaDisableSDEUnitClockGating:bxt */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -126,7 +81,6 @@  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 val;
-	gen9_init_clock_gating(dev_priv);
 
 	/*
 	 * WaDisablePWMClockGating:glk
@@ -8512,7 +8466,6 @@  static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	cnp_init_clock_gating(dev_priv);
-	gen9_init_clock_gating(dev_priv);
 
 	/* WaFbcNukeOnHostModify:cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
@@ -8521,8 +8474,6 @@  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	gen9_init_clock_gating(dev_priv);
-
 	/* WaDisableSDEUnitClockGating:kbl */
 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -8540,8 +8491,6 @@  static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	gen9_init_clock_gating(dev_priv);
-
 	/* WAC6entrylatency:skl */
 	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
 		   FBC_LLC_FULLY_OPEN);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 222f45c..5c9b312 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -573,6 +573,8 @@  static int chv_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 static int gen9_gt_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	GT_WA_SET_BIT(GEN8_CONFIG0, GEN9_DEFAULT_FIXES);
+
 	if (HAS_LLC(dev_priv)) {
 		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 		 *
@@ -833,28 +835,80 @@  static int chv_display_workarounds_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int gen9_display_workarounds_init(struct drm_i915_private *dev_priv)
+{
+	if (HAS_LLC(dev_priv)) {
+		/*
+		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+		 * Display WA#0390: skl,kbl
+		 *
+		 * Must match Sampler, Pixel Back End, and Media. See
+		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+		 */
+		DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, SKL_DE_COMPRESSED_HASH_MODE);
+	}
+
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
+	DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, SKL_EDP_PSR_FIX_RDWRAP);
+
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
+	DISPLAY_WA_SET_BIT(GEN8_CHICKEN_DCPR_1, MASK_WAKEMEM);
+
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
+	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
+	DISPLAY_WA_SET_BIT(DISP_ARB_CTL, DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE);
+
+	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
+	DISPLAY_WA_SET_BIT(ILK_DPFC_CHICKEN, ILK_DPFC_DISABLE_DUMMY0);
+
+	return 0;
+}
+
 static int skl_display_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	int ret = gen9_display_workarounds_init(dev_priv);
+	if (ret)
+		return ret;
+
+	/* WaDisableDopClockGating */
+	DISPLAY_WA_CLR_BIT(GEN7_MISCCPCTL, GEN7_DOP_CLOCK_GATE_ENABLE);
+
 	return 0;
 }
 
 static int bxt_display_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	int ret = gen9_display_workarounds_init(dev_priv);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
 static int kbl_display_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	int ret = gen9_display_workarounds_init(dev_priv);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
 static int glk_display_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	int ret = gen9_display_workarounds_init(dev_priv);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
 static int cfl_display_workarounds_init(struct drm_i915_private *dev_priv)
 {
+	int ret = gen9_display_workarounds_init(dev_priv);
+	if (ret)
+		return ret;
+
 	return 0;
 }