From patchwork Mon Oct 30 20:17:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10033063 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 461CB6039A for ; Mon, 30 Oct 2017 20:17:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A6CE23B34 for ; Mon, 30 Oct 2017 20:17:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F4A028854; Mon, 30 Oct 2017 20:17:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C390023B34 for ; Mon, 30 Oct 2017 20:17:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C67D6E4C0; Mon, 30 Oct 2017 20:17:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F6626E4BF for ; Mon, 30 Oct 2017 20:17:18 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP; 30 Oct 2017 13:17:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,321,1505804400"; d="scan'208";a="169689625" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by fmsmga006.fm.intel.com with ESMTP; 30 Oct 2017 13:17:16 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Oct 2017 13:17:18 -0700 Message-Id: <1509394647-23209-12-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> References: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 11/20] drm/i915/gen9: Move GT and Display workarounds from init_clock_gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To their rightful place inside intel_workarounds.c v2: - Rebase on WA removed - Rebased to carry the init_early nomenclature over (Chris) Signed-off-by: Oscar Mateo Cc: Rodrigo Vivi Cc: Mika Kuoppala Cc: Ville Syrjälä Reviewed-by: Chris Wilson (v1) --- drivers/gpu/drm/i915/intel_pm.c | 48 ----------------------------- drivers/gpu/drm/i915/intel_workarounds.c | 52 ++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ff3ac6c..f712b02 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -57,50 +57,8 @@ #define INTEL_RC6p_ENABLE (1<<1) #define INTEL_RC6pp_ENABLE (1<<2) -static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) -{ - if (HAS_LLC(dev_priv)) { - /* - * WaCompressedResourceDisplayNewHashMode:skl,kbl - * Display WA#0390: skl,kbl - * - * Must match Sampler, Pixel Back End, and Media. See - * WaCompressedResourceSamplerPbeMediaNewHashMode. - */ - I915_WRITE(CHICKEN_PAR1_1, - I915_READ(CHICKEN_PAR1_1) | - SKL_DE_COMPRESSED_HASH_MODE); - } - - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ - I915_WRITE(CHICKEN_PAR1_1, - I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); - - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ - I915_WRITE(GEN8_CHICKEN_DCPR_1, - I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); - - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */ - /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */ - I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | - DISP_FBC_WM_DIS | - DISP_FBC_MEMORY_WAKE); - - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ - I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | - ILK_DPFC_DISABLE_DUMMY0); - - if (IS_SKYLAKE(dev_priv)) { - /* WaDisableDopClockGating */ - I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) - & ~GEN7_DOP_CLOCK_GATE_ENABLE); - } -} - static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) { - gen9_init_clock_gating(dev_priv); - /* WaDisableSDEUnitClockGating:bxt */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); @@ -123,7 +81,6 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) static void glk_init_clock_gating(struct drm_i915_private *dev_priv) { u32 val; - gen9_init_clock_gating(dev_priv); /* * WaDisablePWMClockGating:glk @@ -8522,7 +8479,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) { cnp_init_clock_gating(dev_priv); - gen9_init_clock_gating(dev_priv); /* WaFbcNukeOnHostModify:cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | @@ -8531,8 +8487,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) { - gen9_init_clock_gating(dev_priv); - /* WaDisableSDEUnitClockGating:kbl */ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | @@ -8550,8 +8504,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) static void skl_init_clock_gating(struct drm_i915_private *dev_priv) { - gen9_init_clock_gating(dev_priv); - /* WAC6entrylatency:skl */ I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | FBC_LLC_FULLY_OPEN); diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 82defb1..08b2e8c 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -838,28 +838,80 @@ static int chv_display_workarounds_init_early(struct drm_i915_private *dev_priv) return 0; } +static int gen9_display_workarounds_init_early(struct drm_i915_private *dev_priv) +{ + if (HAS_LLC(dev_priv)) { + /* + * WaCompressedResourceDisplayNewHashMode:skl,kbl + * Display WA#0390: skl,kbl + * + * Must match Sampler, Pixel Back End, and Media. See + * WaCompressedResourceSamplerPbeMediaNewHashMode. + */ + DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, SKL_DE_COMPRESSED_HASH_MODE); + } + + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ + DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, SKL_EDP_PSR_FIX_RDWRAP); + + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ + DISPLAY_WA_SET_BIT(GEN8_CHICKEN_DCPR_1, MASK_WAKEMEM); + + /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */ + /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */ + DISPLAY_WA_SET_BIT(DISP_ARB_CTL, DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE); + + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ + DISPLAY_WA_SET_BIT(ILK_DPFC_CHICKEN, ILK_DPFC_DISABLE_DUMMY0); + + return 0; +} + static int skl_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + int ret = gen9_display_workarounds_init_early(dev_priv); + if (ret) + return ret; + + /* WaDisableDopClockGating */ + DISPLAY_WA_CLR_BIT(GEN7_MISCCPCTL, GEN7_DOP_CLOCK_GATE_ENABLE); + return 0; } static int bxt_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + int ret = gen9_display_workarounds_init_early(dev_priv); + if (ret) + return ret; + return 0; } static int kbl_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + int ret = gen9_display_workarounds_init_early(dev_priv); + if (ret) + return ret; + return 0; } static int glk_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + int ret = gen9_display_workarounds_init_early(dev_priv); + if (ret) + return ret; + return 0; } static int cfl_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + int ret = gen9_display_workarounds_init_early(dev_priv); + if (ret) + return ret; + return 0; }