From patchwork Mon Oct 30 20:17:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10033069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D8386039A for ; Mon, 30 Oct 2017 20:17:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 11E4F23B34 for ; Mon, 30 Oct 2017 20:17:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06CDA28854; Mon, 30 Oct 2017 20:17:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B18B523B34 for ; Mon, 30 Oct 2017 20:17:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 628136E4D7; Mon, 30 Oct 2017 20:17:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 895606E4BE for ; Mon, 30 Oct 2017 20:17:18 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP; 30 Oct 2017 13:17:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,321,1505804400"; d="scan'208";a="169689644" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by fmsmga006.fm.intel.com with ESMTP; 30 Oct 2017 13:17:16 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Oct 2017 13:17:24 -0700 Message-Id: <1509394647-23209-18-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> References: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 17/20] drm/i915/chv: Move GT and Display workarounds from init_clock_gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To their rightful place inside intel_workarounds.c TODO: Notice that we are leaving WaProgramL3SqcReg1Default (and the associated WaTempDisableDOPClkGating) behind because it requires extra careful reviewing. We'll deal with it in a separate patch. v2: Classify WaDisableCSUnitClockGating and WaDisableSDEUnitClockGating as GT WAs Signed-off-by: Oscar Mateo Reviewed-by: Chris Wilson (v1) Cc: Rodrigo Vivi Cc: Mika Kuoppala Cc: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 24 ------------------------ drivers/gpu/drm/i915/intel_workarounds.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ee0e784..b15892b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8707,36 +8707,12 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) static void chv_init_clock_gating(struct drm_i915_private *dev_priv) { - /* WaVSRefCountFullforceMissDisable:chv */ - /* WaDSRefCountFullforceMissDisable:chv */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & - ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); - - /* WaDisableSemaphoreAndSyncFlipWait:chv */ - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - - /* WaDisableCSUnitClockGating:chv */ - I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | - GEN6_CSUNIT_CLOCK_GATE_DISABLE); - - /* WaDisableSDEUnitClockGating:chv */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - /* * WaProgramL3SqcReg1Default:chv * See gfxspecs/Related Documents/Performance Guide/ * LSQC Setting Recommendations. */ gen8_set_l3sqc_credits(dev_priv, 38, 2); - - /* - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. - */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); } static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 71e1858..c0f4513 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -568,6 +568,27 @@ static int bdw_gt_workarounds_init_early(struct drm_i915_private *dev_priv) static int chv_gt_workarounds_init_early(struct drm_i915_private *dev_priv) { + /* WaVSRefCountFullforceMissDisable:chv */ + /* WaDSRefCountFullforceMissDisable:chv */ + GT_WA_CLR_BIT(GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME | + GEN7_FF_VS_REF_CNT_FFME); + + /* WaDisableSemaphoreAndSyncFlipWait:chv */ + GT_WA_SET_BIT_MASKED(GEN6_RC_SLEEP_PSMI_CONTROL, + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + + /* + * GTT cache may not work with big pages, so if those + * are ever enabled GTT cache may need to be disabled. + */ + GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF, GTT_CACHE_EN_ALL); + + /* WaDisableCSUnitClockGating:chv */ + GT_WA_SET_BIT(GEN6_UCGCTL1, GEN6_CSUNIT_CLOCK_GATE_DISABLE); + + /* WaDisableSDEUnitClockGating:chv */ + GT_WA_SET_BIT(GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + return 0; }