From patchwork Mon Oct 30 20:17:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10033097 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D5686039A for ; Mon, 30 Oct 2017 20:18:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 511A227FB1 for ; Mon, 30 Oct 2017 20:18:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45C8628854; Mon, 30 Oct 2017 20:18:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D6C5D27FB1 for ; Mon, 30 Oct 2017 20:18:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA0776E532; Mon, 30 Oct 2017 20:18:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 903026E4BE for ; Mon, 30 Oct 2017 20:17:57 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP; 30 Oct 2017 13:17:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,321,1505804400"; d="scan'208";a="169689648" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by fmsmga006.fm.intel.com with ESMTP; 30 Oct 2017 13:17:16 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Oct 2017 13:17:25 -0700 Message-Id: <1509394647-23209-19-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> References: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Cc: Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH 18/20] drm/i915/bdw: Move GT and Display workarounds from init_clock_gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To their rightful place inside intel_workarounds.c TODO: Notice that we are leaving WaProgramL3SqcReg1Default (and the associated WaTempDisableDOPClkGating) behind because it requires extra careful reviewing. We'll deal with it in a separate patch. TODO2: Decide what to do with lpt_init_clock_gating (shouldn't WADPOClockGatingDisable be marked as "bdw"? shouldn't it be protected by HAS_PCH_LPT_LP? do we want to move the whole thing to the workarounds file or not?). v2: Classify WaDisableSDEUnitClockGating as GT WA Signed-off-by: Oscar Mateo Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Mika Kuoppala Cc: Ville Syrjälä Cc: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 47 -------------------------------- drivers/gpu/drm/i915/intel_workarounds.c | 43 +++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b15892b..f1e3a04 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8419,59 +8419,12 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { - /* The GTT cache must be disabled if the system is using 2M pages. */ - bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, - I915_GTT_PAGE_SIZE_2M); - enum pipe pipe; - ilk_init_lp_watermarks(dev_priv); - /* WaSwitchSolVfFArbitrationPriority:bdw */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); - - /* WaPsrDPAMaskVBlankInSRD:bdw */ - I915_WRITE(CHICKEN_PAR1_1, - I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); - - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ - for_each_pipe(dev_priv, pipe) { - I915_WRITE(CHICKEN_PIPESL_1(pipe), - I915_READ(CHICKEN_PIPESL_1(pipe)) | - BDW_DPRS_MASK_VBLANK_SRD); - } - - /* WaVSRefCountFullforceMissDisable:bdw */ - /* WaDSRefCountFullforceMissDisable:bdw */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & - ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); - - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - - /* WaDisableSDEUnitClockGating:bdw */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - /* WaProgramL3SqcReg1Default:bdw */ gen8_set_l3sqc_credits(dev_priv, 30, 2); - /* WaGttCachingOffByDefault:bdw */ - I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); - - /* WaKVMNotificationOnConfigChange:bdw */ - I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) - | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); - lpt_init_clock_gating(dev_priv); - - /* WaDisableDopClockGating:bdw - * - * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP - * clock gating. - */ - I915_WRITE(GEN6_UCGCTL1, - I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); } static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index c0f4513..0a88c92 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -563,6 +563,28 @@ static int gt_wa_add(struct drm_i915_private *dev_priv, static int bdw_gt_workarounds_init_early(struct drm_i915_private *dev_priv) { + /* The GTT cache must be disabled if the system is using 2M pages. */ + bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M); + + /* WaSwitchSolVfFArbitrationPriority:bdw */ + GT_WA_SET_BIT(GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL); + + /* WaVSRefCountFullforceMissDisable:bdw */ + /* WaDSRefCountFullforceMissDisable:bdw */ + GT_WA_CLR_BIT(GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME | + GEN7_FF_VS_REF_CNT_FFME); + + /* WaDisableSemaphoreAndSyncFlipWait:bdw */ + GT_WA_SET_BIT_MASKED(GEN6_RC_SLEEP_PSMI_CONTROL, + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + + /* WaDisableSDEUnitClockGating:bdw */ + GT_WA_SET_BIT(GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + + /* WaGttCachingOffByDefault:bdw */ + GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF, + can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); + return 0; } @@ -862,6 +884,27 @@ static int display_wa_add(struct drm_i915_private *dev_priv, static int bdw_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + enum pipe pipe; + + /* WaPsrDPAMaskVBlankInSRD:bdw */ + DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, DPA_MASK_VBLANK_SRD); + + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ + for_each_pipe(dev_priv, pipe) { + DISPLAY_WA_SET_BIT(CHICKEN_PIPESL_1(pipe), + BDW_DPRS_MASK_VBLANK_SRD); + } + + /* WaKVMNotificationOnConfigChange:bdw */ + DISPLAY_WA_SET_BIT(CHICKEN_PAR2_1, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); + + /* WaDisableDopClockGating:bdw + * + * Also see the CHICKEN2 write in bdw_gt_workarounds_init() to disable + * DOP clock gating. + */ + DISPLAY_WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); + return 0; }