From patchwork Fri Nov 3 18:09:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10041007 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4A4F5602D8 for ; Fri, 3 Nov 2017 18:10:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F47529730 for ; Fri, 3 Nov 2017 18:10:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 32A98297F2; Fri, 3 Nov 2017 18:10:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD0A029730 for ; Fri, 3 Nov 2017 18:10:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE3F16EB0C; Fri, 3 Nov 2017 18:09:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4254C6EAEF for ; Fri, 3 Nov 2017 18:09:42 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 03 Nov 2017 11:09:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,339,1505804400"; d="scan'208";a="169033975" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by orsmga005.jf.intel.com with ESMTP; 03 Nov 2017 11:09:38 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Nov 2017 11:09:47 -0700 Message-Id: <1509732588-10599-20-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509732588-10599-1-git-send-email-oscar.mateo@intel.com> References: <1509732588-10599-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Cc: Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [RFC PATCH 19/20] drm/i915/bdw: Move GT and Display workarounds from init_clock_gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To their rightful place inside intel_workarounds.c TODO2: Decide what to do with lpt_init_clock_gating (shouldn't WADPOClockGatingDisable be marked as "bdw"? shouldn't it be protected by HAS_PCH_LPT_LP? do we want to move the whole thing to the workarounds file or not?). v2: Classify WaDisableSDEUnitClockGating as GT WA v3: - Static tables (Joonas) - Also move WaProgramL3SqcReg1Default/WaTempDisableDOPClkGating Signed-off-by: Oscar Mateo Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Mika Kuoppala Cc: Ville Syrjälä Cc: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 76 ------------------------------ drivers/gpu/drm/i915/intel_workarounds.c | 81 +++++++++++++++++++++++++++++--- 2 files changed, 74 insertions(+), 83 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aef0aee..0fc0670 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8391,87 +8391,11 @@ static void lpt_suspend_hw(struct drm_i915_private *dev_priv) } } -static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, - int general_prio_credits, - int high_prio_credits) -{ - u32 misccpctl; - u32 val; - - /* WaTempDisableDOPClkGating:bdw */ - misccpctl = I915_READ(GEN7_MISCCPCTL); - I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); - - val = I915_READ(GEN8_L3SQCREG1); - val &= ~L3_PRIO_CREDITS_MASK; - val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); - val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); - I915_WRITE(GEN8_L3SQCREG1, val); - - /* - * Wait at least 100 clocks before re-enabling clock gating. - * See the definition of L3SQCREG1 in BSpec. - */ - POSTING_READ(GEN8_L3SQCREG1); - udelay(1); - I915_WRITE(GEN7_MISCCPCTL, misccpctl); -} - static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { - /* The GTT cache must be disabled if the system is using 2M pages. */ - bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, - I915_GTT_PAGE_SIZE_2M); - enum pipe pipe; - ilk_init_lp_watermarks(dev_priv); - /* WaSwitchSolVfFArbitrationPriority:bdw */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); - - /* WaPsrDPAMaskVBlankInSRD:bdw */ - I915_WRITE(CHICKEN_PAR1_1, - I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); - - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ - for_each_pipe(dev_priv, pipe) { - I915_WRITE(CHICKEN_PIPESL_1(pipe), - I915_READ(CHICKEN_PIPESL_1(pipe)) | - BDW_DPRS_MASK_VBLANK_SRD); - } - - /* WaVSRefCountFullforceMissDisable:bdw */ - /* WaDSRefCountFullforceMissDisable:bdw */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & - ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); - - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - - /* WaDisableSDEUnitClockGating:bdw */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - - /* WaProgramL3SqcReg1Default:bdw */ - gen8_set_l3sqc_credits(dev_priv, 30, 2); - - /* WaGttCachingOffByDefault:bdw */ - I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); - - /* WaKVMNotificationOnConfigChange:bdw */ - I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) - | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); - lpt_init_clock_gating(dev_priv); - - /* WaDisableDopClockGating:bdw - * - * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP - * clock gating. - */ - I915_WRITE(GEN6_UCGCTL1, - I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); } static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 1ebce4f..a8fe655 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -643,9 +643,6 @@ static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv, return total_count; } -static struct i915_wa_reg gen8_gt_was[] = { -}; - /* WaTempDisableDOPClkGating */ static bool disable_dop_clock_gating(struct drm_i915_private *dev_priv, struct i915_wa_reg *wa) @@ -673,7 +670,45 @@ static void enable_dop_clock_gating(struct drm_i915_private *dev_priv, I915_WRITE(GEN7_MISCCPCTL, misccpctl); } +static bool use_gtt_cache(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa) +{ + /* The GTT cache must be disabled if the system is using 2M pages. */ + bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M); + + wa->value = can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0; + + return true; +} + static struct i915_wa_reg bdw_gt_was[] = { + { WA_GT("WaSwitchSolVfFArbitrationPriority"), + ALL_REVS, REG(GAM_ECOCHK), + SET_BIT(HSW_ECOCHK_ARB_PRIO_SOL) }, + + { WA_GT("WaVSRefCountFullforceMissDisable + WaDSRefCountFullforceMissDisable"), + ALL_REVS, REG(GEN7_FF_THREAD_MODE), + CLEAR_BIT(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME) }, + + { WA_GT(""), + ALL_REVS, REG(GEN6_RC_SLEEP_PSMI_CONTROL), + SET_BIT_MASKED(GEN8_RC_SEMA_IDLE_MSG_DISABLE) }, + + { WA_GT("WaDisableSDEUnitClockGating"), + ALL_REVS, REG(GEN8_UCGCTL6), + SET_BIT(GEN8_SDEUNIT_CLOCK_GATE_DISABLE) }, + + { WA_GT("WaProgramL3SqcReg1Default"), + ALL_REVS, REG(GEN8_L3SQCREG1), + SET_FIELD(L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(30) | L3_HIGH_PRIO_CREDITS(2)), + .pre_hook = disable_dop_clock_gating, + .post_hook = enable_dop_clock_gating }, + + { WA_GT("WaGttCachingOffByDefault"), + ALL_REVS, REG(HSW_GTT_CACHE_EN), + SET_FIELD(0xFFFFFFFF, 0x0), + .pre_hook = use_gtt_cache }, }; static struct i915_wa_reg chv_gt_was[] = { @@ -860,7 +895,6 @@ static void enable_dop_clock_gating(struct drm_i915_private *dev_priv, }; static const struct i915_wa_reg_table bdw_gt_wa_tbl[] = { - { gen8_gt_was, ARRAY_SIZE(gen8_gt_was) }, { bdw_gt_was, ARRAY_SIZE(bdw_gt_was) }, }; @@ -947,10 +981,44 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count); } -static struct i915_wa_reg gen8_disp_was[] = { -}; +static bool has_pipe(struct drm_i915_private *dev_priv, struct i915_wa_reg *wa) +{ + enum pipe pipe = wa->hook_data; + + return (INTEL_INFO(dev_priv)->num_pipes > pipe); +} static struct i915_wa_reg bdw_disp_was[] = { + { WA_DISP("WaPsrDPAMaskVBlankInSRD"), + ALL_REVS, REG(CHICKEN_PAR1_1), + SET_BIT(DPA_MASK_VBLANK_SRD) }, + + { WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe A)"), + ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_A)), + SET_BIT(BDW_DPRS_MASK_VBLANK_SRD), + .hook_data = PIPE_A, .pre_hook = has_pipe }, + + { WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe B)"), + ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_B)), + SET_BIT(BDW_DPRS_MASK_VBLANK_SRD), + .hook_data = PIPE_B, .pre_hook = has_pipe }, + + { WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe C)"), + ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_C)), + SET_BIT(BDW_DPRS_MASK_VBLANK_SRD), + .hook_data = PIPE_C, .pre_hook = has_pipe }, + + { WA_DISP("WaKVMNotificationOnConfigChange"), + ALL_REVS, REG(CHICKEN_PAR2_1), + SET_BIT(KVM_CONFIG_CHANGE_NOTIFICATION_SELECT) }, + + /* + * Also see the CHICKEN2 write in bdw_gt_was to disable DOP + * clock gating. + */ + { WA_DISP("WaDisableDopClockGating"), + ALL_REVS, REG(GEN6_UCGCTL1), + SET_BIT(GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE) }, }; static struct i915_wa_reg gen9_disp_was[] = { @@ -1076,7 +1144,6 @@ static bool has_pch_cnp(struct drm_i915_private *dev_priv, }; static const struct i915_wa_reg_table bdw_disp_wa_tbl[] = { - { gen8_disp_was, ARRAY_SIZE(gen8_disp_was) }, { bdw_disp_was, ARRAY_SIZE(bdw_disp_was) }, };