diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aef0aee..0fc0670 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8391,87 +8391,11 @@ static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
-				   int general_prio_credits,
-				   int high_prio_credits)
-{
-	u32 misccpctl;
-	u32 val;
-
-	/* WaTempDisableDOPClkGating:bdw */
-	misccpctl = I915_READ(GEN7_MISCCPCTL);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-
-	val = I915_READ(GEN8_L3SQCREG1);
-	val &= ~L3_PRIO_CREDITS_MASK;
-	val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
-	val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
-	I915_WRITE(GEN8_L3SQCREG1, val);
-
-	/*
-	 * Wait at least 100 clocks before re-enabling clock gating.
-	 * See the definition of L3SQCREG1 in BSpec.
-	 */
-	POSTING_READ(GEN8_L3SQCREG1);
-	udelay(1);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
-}
-
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* The GTT cache must be disabled if the system is using 2M pages. */
-	bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-						 I915_GTT_PAGE_SIZE_2M);
-	enum pipe pipe;
-
 	ilk_init_lp_watermarks(dev_priv);
 
-	/* WaSwitchSolVfFArbitrationPriority:bdw */
-	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
-
-	/* WaPsrDPAMaskVBlankInSRD:bdw */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
-
-	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
-	for_each_pipe(dev_priv, pipe) {
-		I915_WRITE(CHICKEN_PIPESL_1(pipe),
-			   I915_READ(CHICKEN_PIPESL_1(pipe)) |
-			   BDW_DPRS_MASK_VBLANK_SRD);
-	}
-
-	/* WaVSRefCountFullforceMissDisable:bdw */
-	/* WaDSRefCountFullforceMissDisable:bdw */
-	I915_WRITE(GEN7_FF_THREAD_MODE,
-		   I915_READ(GEN7_FF_THREAD_MODE) &
-		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
-
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
-	/* WaDisableSDEUnitClockGating:bdw */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-	/* WaProgramL3SqcReg1Default:bdw */
-	gen8_set_l3sqc_credits(dev_priv, 30, 2);
-
-	/* WaGttCachingOffByDefault:bdw */
-	I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
-	/* WaKVMNotificationOnConfigChange:bdw */
-	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
-		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
-
 	lpt_init_clock_gating(dev_priv);
-
-	/* WaDisableDopClockGating:bdw
-	 *
-	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
-	 * clock gating.
-	 */
-	I915_WRITE(GEN6_UCGCTL1,
-		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 1ebce4f..a8fe655 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -643,9 +643,6 @@ static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv,
 	return total_count;
 }
 
-static struct i915_wa_reg gen8_gt_was[] = {
-};
-
 /* WaTempDisableDOPClkGating */
 static bool disable_dop_clock_gating(struct drm_i915_private *dev_priv,
                         	     struct i915_wa_reg *wa)
@@ -673,7 +670,45 @@ static void enable_dop_clock_gating(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static bool use_gtt_cache(struct drm_i915_private *dev_priv,
+			  struct i915_wa_reg *wa)
+{
+	/* The GTT cache must be disabled if the system is using 2M pages. */
+	bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M);
+
+	wa->value = can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0;
+
+	return true;
+}
+
 static struct i915_wa_reg bdw_gt_was[] = {
+	{ WA_GT("WaSwitchSolVfFArbitrationPriority"),
+	  ALL_REVS, REG(GAM_ECOCHK),
+	  SET_BIT(HSW_ECOCHK_ARB_PRIO_SOL) },
+
+	{ WA_GT("WaVSRefCountFullforceMissDisable + WaDSRefCountFullforceMissDisable"),
+	  ALL_REVS, REG(GEN7_FF_THREAD_MODE),
+	  CLEAR_BIT(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME) },
+
+	{ WA_GT(""),
+	  ALL_REVS, REG(GEN6_RC_SLEEP_PSMI_CONTROL),
+	  SET_BIT_MASKED(GEN8_RC_SEMA_IDLE_MSG_DISABLE) },
+
+	{ WA_GT("WaDisableSDEUnitClockGating"),
+	  ALL_REVS, REG(GEN8_UCGCTL6),
+	  SET_BIT(GEN8_SDEUNIT_CLOCK_GATE_DISABLE) },
+
+	{ WA_GT("WaProgramL3SqcReg1Default"),
+	  ALL_REVS, REG(GEN8_L3SQCREG1),
+	  SET_FIELD(L3_PRIO_CREDITS_MASK,
+		    L3_GENERAL_PRIO_CREDITS(30) | L3_HIGH_PRIO_CREDITS(2)),
+	  .pre_hook = disable_dop_clock_gating,
+	  .post_hook = enable_dop_clock_gating },
+
+	{ WA_GT("WaGttCachingOffByDefault"),
+	  ALL_REVS, REG(HSW_GTT_CACHE_EN),
+	  SET_FIELD(0xFFFFFFFF, 0x0),
+	  .pre_hook = use_gtt_cache },
 };
 
 static struct i915_wa_reg chv_gt_was[] = {
@@ -860,7 +895,6 @@ static void enable_dop_clock_gating(struct drm_i915_private *dev_priv,
 };
 
 static const struct i915_wa_reg_table bdw_gt_wa_tbl[] = {
-	{ gen8_gt_was, ARRAY_SIZE(gen8_gt_was) },
 	{ bdw_gt_was,  ARRAY_SIZE(bdw_gt_was) },
 };
 
@@ -947,10 +981,44 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count);
 }
 
-static struct i915_wa_reg gen8_disp_was[] = {
-};
+static bool has_pipe(struct drm_i915_private *dev_priv, struct i915_wa_reg *wa)
+{
+	enum pipe pipe = wa->hook_data;
+
+	return (INTEL_INFO(dev_priv)->num_pipes > pipe);
+}
 
 static struct i915_wa_reg bdw_disp_was[] = {
+	{ WA_DISP("WaPsrDPAMaskVBlankInSRD"),
+	  ALL_REVS, REG(CHICKEN_PAR1_1),
+	  SET_BIT(DPA_MASK_VBLANK_SRD) },
+
+	{ WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe A)"),
+	  ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_A)),
+	  SET_BIT(BDW_DPRS_MASK_VBLANK_SRD),
+	  .hook_data = PIPE_A, .pre_hook = has_pipe },
+
+	{ WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe B)"),
+	  ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_B)),
+	  SET_BIT(BDW_DPRS_MASK_VBLANK_SRD),
+	  .hook_data = PIPE_B, .pre_hook = has_pipe },
+
+	{ WA_DISP("WaPsrDPRSUnmaskVBlankInSRD (pipe C)"),
+	  ALL_REVS, REG(CHICKEN_PIPESL_1(PIPE_C)),
+	  SET_BIT(BDW_DPRS_MASK_VBLANK_SRD),
+	  .hook_data = PIPE_C, .pre_hook = has_pipe },
+
+	{ WA_DISP("WaKVMNotificationOnConfigChange"),
+	  ALL_REVS, REG(CHICKEN_PAR2_1),
+	  SET_BIT(KVM_CONFIG_CHANGE_NOTIFICATION_SELECT) },
+
+	/*
+	 * Also see the CHICKEN2 write in bdw_gt_was to disable DOP
+	 * clock gating.
+	 */
+	{ WA_DISP("WaDisableDopClockGating"),
+	  ALL_REVS, REG(GEN6_UCGCTL1),
+	  SET_BIT(GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE) },
 };
 
 static struct i915_wa_reg gen9_disp_was[] = {
@@ -1076,7 +1144,6 @@ static bool has_pch_cnp(struct drm_i915_private *dev_priv,
 };
 
 static const struct i915_wa_reg_table bdw_disp_wa_tbl[] = {
-	{ gen8_disp_was, ARRAY_SIZE(gen8_disp_was) },
 	{ bdw_disp_was,  ARRAY_SIZE(bdw_disp_was) },
 };
 
