From patchwork Fri Nov 3 20:43:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10041187 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 03B896032D for ; Fri, 3 Nov 2017 20:43:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E9E1429931 for ; Fri, 3 Nov 2017 20:43:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DE94129936; Fri, 3 Nov 2017 20:43:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ECDBC29931 for ; Fri, 3 Nov 2017 20:43:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CA846E0F7; Fri, 3 Nov 2017 20:43:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A3DF16E0F7 for ; Fri, 3 Nov 2017 20:43:05 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Nov 2017 13:43:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,339,1505804400"; d="scan'208";a="917385471" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by FMSMGA003.fm.intel.com with ESMTP; 03 Nov 2017 13:43:05 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Nov 2017 13:43:07 -0700 Message-Id: <1509741787-17441-1-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509732588-10599-7-git-send-email-oscar.mateo@intel.com> References: <1509732588-10599-7-git-send-email-oscar.mateo@intel.com> Subject: [Intel-gfx] [RFC PATCH v2] drm/i915: Transform Whitelist WAs into static tables X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This is for WAs that whitelist a register. v2: Warn about olden GENs in the apply, not in the get function Suggested-by: Joonas Lahtinen Signed-off-by: Oscar Mateo Cc: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_workarounds.c | 251 ++++++++++++++++--------------- drivers/gpu/drm/i915/intel_workarounds.h | 3 + 3 files changed, 131 insertions(+), 125 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e68edf18..441d92e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1991,6 +1991,8 @@ struct i915_wa_reg { u8 since; u8 until; + i915_reg_t whitelist_addr; + i915_reg_t addr; u32 mask; u32 value; diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index b07fbd0..efa6bc2 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -33,6 +33,10 @@ .name = (wa), \ .type = I915_WA_TYPE_GT +#define WA_WHITELIST(wa) \ + .name = (wa), \ + .type = I915_WA_TYPE_WHITELIST + #define ALL_REVS \ .since = 0, \ .until = REVID_FOREVER @@ -75,6 +79,9 @@ .value = MASK(m, v), \ .is_masked_reg = true +#define WHITELIST(reg) \ + .whitelist_addr = reg + static struct i915_wa_reg gen8_ctx_was[] = { { WA_CTX(""), ALL_REVS, REG(INSTPM), @@ -861,160 +868,154 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count); } -static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, - i915_reg_t reg) -{ - struct drm_i915_private *dev_priv = engine->i915; - struct i915_workarounds *wa = &dev_priv->workarounds; - const uint32_t index = wa->hw_whitelist_count[engine->id]; - - if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) - return -EINVAL; +static struct i915_wa_reg gen9_whitelist_was[] = { + { WA_WHITELIST("WaVFEStateAfterPipeControlwithMediaStateClear"), + ALL_REVS, WHITELIST(GEN9_CTX_PREEMPT_REG) }, - I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), - i915_mmio_reg_offset(reg)); - wa->hw_whitelist_count[engine->id]++; + { WA_WHITELIST("WaEnablePreemptionGranularityControlByUMD"), + ALL_REVS, WHITELIST(GEN8_CS_CHICKEN1) }, - return 0; -} - -static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - int ret; + { WA_WHITELIST("WaAllowUMDToModifyHDCChicken1"), + ALL_REVS, WHITELIST(GEN8_HDC_CHICKEN1) }, +}; - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ - ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); - if (ret) - return ret; +static struct i915_wa_reg skl_whitelist_was[] = { + { WA_WHITELIST("WaDisableLSQCROPERFforOCL"), + ALL_REVS, WHITELIST(GEN8_L3SQCREG4) }, +}; - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ - ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); - if (ret) - return ret; +static struct i915_wa_reg bxt_whitelist_was[] = { + { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +" + "WaDisableObjectLevelPreemptionForInstancedDraw +" + "WaDisableObjectLevelPreemtionForInstanceId +" + "WaDisableLSQCROPERFforOCL"), + REVS(0, BXT_REVID_A1), WHITELIST(GEN9_CS_DEBUG_MODE1) }, - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ - ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); - if (ret) - return ret; + { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +" + "WaDisableObjectLevelPreemptionForInstancedDraw +" + "WaDisableObjectLevelPreemtionForInstanceId +" + "WaDisableLSQCROPERFforOCL"), + REVS(0, BXT_REVID_A1), WHITELIST(GEN8_L3SQCREG4) }, +}; - return 0; -} +static struct i915_wa_reg kbl_whitelist_was[] = { + { WA_WHITELIST("WaDisableLSQCROPERFforOCL"), + ALL_REVS, WHITELIST(GEN8_L3SQCREG4) }, +}; -static int skl_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - int ret = gen9_whitelist_workarounds_apply(engine); - if (ret) - return ret; +static struct i915_wa_reg cnl_whitelist_was[] = { + { WA_WHITELIST("WaEnablePreemptionGranularityControlByUMD"), + ALL_REVS, WHITELIST(GEN8_CS_CHICKEN1) }, +}; - /* WaDisableLSQCROPERFforOCL:skl */ - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; +static const struct i915_wa_reg_table skl_whitelist_wa_tbl[] = { + { gen9_whitelist_was, ARRAY_SIZE(gen9_whitelist_was) }, + { skl_whitelist_was, ARRAY_SIZE(skl_whitelist_was) }, +}; - return 0; -} +static const struct i915_wa_reg_table bxt_whitelist_wa_tbl[] = { + { gen9_whitelist_was, ARRAY_SIZE(gen9_whitelist_was) }, + { bxt_whitelist_was, ARRAY_SIZE(bxt_whitelist_was) }, +}; -static int bxt_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; +static const struct i915_wa_reg_table kbl_whitelist_wa_tbl[] = { + { gen9_whitelist_was, ARRAY_SIZE(gen9_whitelist_was) }, + { kbl_whitelist_was, ARRAY_SIZE(kbl_whitelist_was) }, +}; - int ret = gen9_whitelist_workarounds_apply(engine); - if (ret) - return ret; +static const struct i915_wa_reg_table glk_whitelist_wa_tbl[] = { + { gen9_whitelist_was, ARRAY_SIZE(gen9_whitelist_was) }, +}; - /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ - /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ - /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ - /* WaDisableLSQCROPERFforOCL:bxt */ - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { - ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); - if (ret) - return ret; - - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; - } +static const struct i915_wa_reg_table cfl_whitelist_wa_tbl[] = { + { gen9_whitelist_was, ARRAY_SIZE(gen9_whitelist_was) }, +}; - return 0; -} +static const struct i915_wa_reg_table cnl_whitelist_wa_tbl[] = { + { cnl_whitelist_was, ARRAY_SIZE(cnl_whitelist_was) }, +}; -static int kbl_whitelist_workarounds_apply(struct intel_engine_cs *engine) +void intel_whitelist_workarounds_get(struct drm_i915_private *dev_priv, + const struct i915_wa_reg_table **wa_table, + uint *table_count) { - int ret = gen9_whitelist_workarounds_apply(engine); - if (ret) - return ret; - - /* WaDisableLSQCROPERFforOCL:kbl */ - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); - if (ret) - return ret; + *wa_table = NULL; + *table_count = 0; - return 0; + if (INTEL_GEN(dev_priv) < 9) + return; + else if (IS_SKYLAKE(dev_priv)) { + *wa_table = skl_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(skl_whitelist_wa_tbl); + } else if (IS_BROXTON(dev_priv)) { + *wa_table = bxt_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(bxt_whitelist_wa_tbl); + } else if (IS_KABYLAKE(dev_priv)) { + *wa_table = kbl_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(kbl_whitelist_wa_tbl); + } else if (IS_GEMINILAKE(dev_priv)) { + *wa_table = glk_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(glk_whitelist_wa_tbl); + } else if (IS_COFFEELAKE(dev_priv)) { + *wa_table = cfl_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(cfl_whitelist_wa_tbl); + } else if (IS_CANNONLAKE(dev_priv)) { + *wa_table = cnl_whitelist_wa_tbl; + *table_count = ARRAY_SIZE(cnl_whitelist_wa_tbl); + } else { + MISSING_CASE(INTEL_GEN(dev_priv)); + return; + } } -static int glk_whitelist_workarounds_apply(struct intel_engine_cs *engine) +int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine) { - int ret = gen9_whitelist_workarounds_apply(engine); - if (ret) - return ret; - - return 0; -} + struct drm_i915_private *dev_priv = engine->i915; + const struct i915_wa_reg_table *wa_table; + uint table_count, total_count = 0; + int i, j; -static int cfl_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - int ret = gen9_whitelist_workarounds_apply(engine); - if (ret) - return ret; + if (INTEL_GEN(dev_priv) < 9) { + WARN(1, "No whitelisting in Gen%u\n", INTEL_GEN(dev_priv)); + return -EINVAL; + } - return 0; -} + intel_whitelist_workarounds_get(dev_priv, &wa_table, &table_count); -static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - int ret; + for (i = 0; i < table_count; i++) { + struct i915_wa_reg *wa = wa_table[i].table; - /* WaEnablePreemptionGranularityControlByUMD:cnl */ - ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); - if (ret) - return ret; + for (j = 0; j < wa_table[i].count; j++) { + wa[j].applied = + IS_REVID(dev_priv, wa[j].since, wa[j].until); - return 0; -} + if (wa[j].applied && wa[j].pre_hook) + wa[j].applied = wa[j].pre_hook(dev_priv, &wa[j]); -int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - int err; + if (wa[j].applied) { + if (WARN_ON(total_count >= RING_MAX_NONPRIV_SLOTS)) { + wa[j].applied = false; + return -EINVAL; + } - WARN_ON(engine->id != RCS); + /* Cache the translation of the */ + wa[j].addr = + RING_FORCE_TO_NONPRIV(engine->mmio_base, + total_count++); + wa[j].value = + i915_mmio_reg_offset(wa[j].whitelist_addr); + wa[j].mask = 0xffffffff; - dev_priv->workarounds.hw_whitelist_count[engine->id] = 0; + I915_WRITE(wa[j].addr, wa[j].value); + } - if (INTEL_GEN(dev_priv) < 9) { - WARN(1, "No whitelisting in Gen%u\n", INTEL_GEN(dev_priv)); - err = 0; - } else if (IS_SKYLAKE(dev_priv)) - err = skl_whitelist_workarounds_apply(engine); - else if (IS_BROXTON(dev_priv)) - err = bxt_whitelist_workarounds_apply(engine); - else if (IS_KABYLAKE(dev_priv)) - err = kbl_whitelist_workarounds_apply(engine); - else if (IS_GEMINILAKE(dev_priv)) - err = glk_whitelist_workarounds_apply(engine); - else if (IS_COFFEELAKE(dev_priv)) - err = cfl_whitelist_workarounds_apply(engine); - else if (IS_CANNONLAKE(dev_priv)) - err = cnl_whitelist_workarounds_apply(engine); - else { - MISSING_CASE(INTEL_GEN(dev_priv)); - err = 0; + GEM_BUG_ON(wa[j].post_hook); + } } - if (err) - return err; - DRM_DEBUG_DRIVER("%s: Number of whitelist w/a: %d\n", engine->name, - dev_priv->workarounds.hw_whitelist_count[engine->id]); + dev_priv->workarounds.hw_whitelist_count[engine->id] = total_count; + DRM_DEBUG_DRIVER("%s: Number of whitelist w/a: %u\n", engine->name, + total_count); + return 0; } diff --git a/drivers/gpu/drm/i915/intel_workarounds.h b/drivers/gpu/drm/i915/intel_workarounds.h index 9bb3c48..f60913f 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.h +++ b/drivers/gpu/drm/i915/intel_workarounds.h @@ -35,6 +35,9 @@ void intel_gt_workarounds_get(struct drm_i915_private *dev_priv, uint *table_count); void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv); +void intel_whitelist_workarounds_get(struct drm_i915_private *dev_priv, + const struct i915_wa_reg_table **wa_table, + uint *table_count); int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine); #endif