| Message ID | 1511880305-12166-1-git-send-email-valtteri.rantala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 28, 2017 at 02:45:05PM +0000, Valtteri Rantala wrote: > Testing the texture read performance shows that the same tuning for > the SQ credits is needed on GLK as on BXT/APL. This has been also > confirmed by Altug from the HW team. > > V4: Rebase + fix > Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index fede62d..0b04ca7 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ > + if (IS_GEN9_LP(dev_priv)) { > + u32 val = I915_READ(GEN8_L3SQCREG1); > + > + val &= ~L3_PRIO_CREDITS_MASK; > + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); > + I915_WRITE(GEN8_L3SQCREG1, val); > + } > + > /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > @@ -1184,7 +1193,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) > static int bxt_init_workarounds(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > - u32 val; > int ret; > > ret = gen9_init_workarounds(engine); > @@ -1199,12 +1207,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(FF_SLICE_CS_CHICKEN2, > _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); > > - /* WaProgramL3SqcReg1DefaultForPerf:bxt */ > - val = I915_READ(GEN8_L3SQCREG1); > - val &= ~L3_PRIO_CREDITS_MASK; > - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); > - I915_WRITE(GEN8_L3SQCREG1, val); > - > /* WaToEnableHwFixForPushConstHWBug:bxt */ > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Nov 29, 2017 at 07:52:43AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too (rev4) > URL : https://patchwork.freedesktop.org/series/33772/ > State : success Thanks for the patch and reviews, pushed to drm-tip. For the future please keep the whole revision history in the commit log and any Cc: lines and earlier r-bs with version tags if needed (unless the patch changed substantially from the reviewed one). Also please use git format-patch --in-reply-to pointing to the previous version when submitting single patches. > > == Summary == > > Blacklisted hosts: > shard-hsw total:2626 pass:1506 dwarn:11 dfail:0 fail:11 skip:1097 time:9023s > shard-snb total:2520 pass:1218 dwarn:13 dfail:6 fail:7 skip:1270 time:6556s > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7324/shards.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index fede62d..0b04ca7 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ + if (IS_GEN9_LP(dev_priv)) { + u32 val = I915_READ(GEN8_L3SQCREG1); + + val &= ~L3_PRIO_CREDITS_MASK; + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); + I915_WRITE(GEN8_L3SQCREG1, val); + } + /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); @@ -1184,7 +1193,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) static int bxt_init_workarounds(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - u32 val; int ret; ret = gen9_init_workarounds(engine); @@ -1199,12 +1207,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(FF_SLICE_CS_CHICKEN2, _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); - /* WaProgramL3SqcReg1DefaultForPerf:bxt */ - val = I915_READ(GEN8_L3SQCREG1); - val &= ~L3_PRIO_CREDITS_MASK; - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); - I915_WRITE(GEN8_L3SQCREG1, val); - /* WaToEnableHwFixForPushConstHWBug:bxt */ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
Testing the texture read performance shows that the same tuning for the SQ credits is needed on GLK as on BXT/APL. This has been also confirmed by Altug from the HW team. V4: Rebase + fix Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)