From patchwork Fri Feb 2 22:09:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 10198175 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B4CF560388 for ; Fri, 2 Feb 2018 22:15:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A69528F7C for ; Fri, 2 Feb 2018 22:15:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F17928F92; Fri, 2 Feb 2018 22:15:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2FEAB28F7C for ; Fri, 2 Feb 2018 22:15:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B69356F160; Fri, 2 Feb 2018 22:15:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94B976F161 for ; Fri, 2 Feb 2018 22:15:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Feb 2018 14:15:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,451,1511856000"; d="scan'208";a="24317142" Received: from mint-dev.iind.intel.com ([10.223.25.164]) by orsmga003.jf.intel.com with ESMTP; 02 Feb 2018 14:15:03 -0800 From: Ramalingam C To: intel-gfx@lists.freedesktop.org, seanpaul@chromium.org Date: Sat, 3 Feb 2018 03:39:08 +0530 Message-Id: <1517609350-10698-7-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517609350-10698-1-git-send-email-ramalingam.c@intel.com> References: <1517609350-10698-1-git-send-email-ramalingam.c@intel.com> Subject: [Intel-gfx] [PATCH v3 6/8] drm/i915: Detect panel's hdcp capability X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.vetter@ffwll.ch, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP DP HDCP1.4 spec mandates that An can be written to panel only after detecting the panel's hdcp capability. For DP 0th Bit of Bcaps register indicates the panel's hdcp capability For HDMI valid BKSV indicates the panel's hdcp capability. For HDMI it is optional to detect the panel's hdcp capability before An Write. v2: Added comments explaining the need for action [Seanpaul]. Made panel's hdcp capability detection optional for hdmi [Seanpaul]. Defined a func for reading bcaps for DP [Seanpaul]. v3: Removed the NULL initialization [Seanpaul]. Signed-off-by: Ramalingam C Reviewed-by: Sean Paul --- drivers/gpu/drm/i915/intel_dp.c | 39 +++++++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_hdcp.c | 18 +++++++++++++++++- 3 files changed, 56 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 03d86ff9b805..5fa6bb7dbb7a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5107,17 +5107,32 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, - bool *repeater_present) +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, + u8 *bcaps) { ssize_t ret; - u8 bcaps; + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, - &bcaps, 1); + bcaps, 1); if (ret != 1) { DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; } + + return 0; +} + +static +int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, + bool *repeater_present) +{ + ssize_t ret; + u8 bcaps; + + ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + if (ret) + return ret; + *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; return 0; } @@ -5218,6 +5233,21 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); } +static +int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, + bool *hdcp_capable) +{ + ssize_t ret; + u8 bcaps; + + ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + if (ret) + return ret; + + *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; + return 0; +} + static const struct intel_hdcp_shim intel_dp_hdcp_shim = { .write_an_aksv = intel_dp_hdcp_write_an_aksv, .read_bksv = intel_dp_hdcp_read_bksv, @@ -5229,6 +5259,7 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, .toggle_signalling = intel_dp_hdcp_toggle_signalling, .check_link = intel_dp_hdcp_check_link, + .hdcp_capable = intel_dp_hdcp_capable, }; static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d6a808374dfb..468ec1e90e16 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -369,6 +369,10 @@ struct intel_hdcp_shim { /* Ensures the link is still protected */ bool (*check_link)(struct intel_digital_port *intel_dig_port); + + /* Detects panel's hdcp capability. This is optional for HDMI. */ + int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, + bool *hdcp_capable); }; struct intel_connector { diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index 65bdb95c0ad7..7ae8d83760ed 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -414,12 +414,28 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port, u32 reg; u8 shim[DRM_HDCP_RI_LEN]; } ri; - bool repeater_present; + bool repeater_present, hdcp_capable; dev_priv = intel_dig_port->base.base.dev->dev_private; port = intel_dig_port->base.port; + /* + * Detects whether the display is HDCP capable. Although we check for + * valid Bksv below, the HDCP over DP spec requires that we check + * whether the display supports HDCP before we write An. For HDMI + * displays, this is not necessary. + */ + if (shim->hdcp_capable) { + ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); + if (ret) + return ret; + if (!hdcp_capable) { + DRM_ERROR("Panel is not HDCP capable\n"); + return -EINVAL; + } + } + /* Initialize An with 2 random values and acquire it */ for (i = 0; i < 2; i++) I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());