| Message ID | 1517921899-25926-4-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > Add support of recognizing DRM_FORMAT_NV12 from plane_format > register value. > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 60ba5bb..e3a6a7f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) > switch (format) { > case PLANE_CTL_FORMAT_RGB_565: > return DRM_FORMAT_RGB565; > + case PLANE_CTL_FORMAT_NV12: > + return DRM_FORMAT_NV12; I dont think this is correct, the case PLANE_CTL_FORMAT_NV12 is defined as (1 << 24) but when I check bspec definition, 24th bit is set for P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This means we have mixed NV12 format with P0xx formats. When I checked the definition of DRM_FORMAT_NV12, I am not sure if that's intended for this. Ville, I saw that the DRM_FORMAT_NV12 definition was added by you, can you please comment if this is the right usage ? - Shashank > default: > case PLANE_CTL_FORMAT_XRGB_8888: > if (rgb_order) {
> -----Original Message----- > From: Sharma, Shashank > Sent: Wednesday, February 7, 2018 9:22 PM > To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil > <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>; > Kumar, Mahesh1 <mahesh1.kumar@intel.com> > Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in > skl_format_to_fourcc > > Regards > > Shashank > > > On 2/6/2018 6:28 PM, Vidya Srinivas wrote: > > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > > > Add support of recognizing DRM_FORMAT_NV12 from plane_format > register > > value. > > > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > > --- > > drivers/gpu/drm/i915/intel_display.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 60ba5bb..e3a6a7f 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool > rgb_order, bool alpha) > > switch (format) { > > case PLANE_CTL_FORMAT_RGB_565: > > return DRM_FORMAT_RGB565; > > + case PLANE_CTL_FORMAT_NV12: > > + return DRM_FORMAT_NV12; > I dont think this is correct, the case PLANE_CTL_FORMAT_NV12 is defined as > (1 << 24) but when I check bspec definition, 24th bit is set for > P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are > 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This means we > have mixed NV12 format with P0xx formats. When I checked the definition > of DRM_FORMAT_NV12, I am not sure if that's intended for this. Ville, I saw > that the DRM_FORMAT_NV12 definition was added by you, can you please > comment if this is the right usage ? > Upto Gen10 24-27 bits of PLANE_CTL will be used for format. ICL onwards 23rd bit is also used. PLANE_CTL_FORMAT_MASK has been defined in i915_reg.h and mapping will be same if 23rd bit is 0. For NV12, 1<< 24 thus holds good for all Gen. > > default: > > case PLANE_CTL_FORMAT_XRGB_8888: > > if (rgb_order) {
On 2/8/2018 8:50 AM, Srinivas, Vidya wrote: > >> -----Original Message----- >> From: Sharma, Shashank >> Sent: Wednesday, February 7, 2018 9:22 PM >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel- >> gfx@lists.freedesktop.org >> Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil >> <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>; >> Kumar, Mahesh1 <mahesh1.kumar@intel.com> >> Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in >> skl_format_to_fourcc >> >> Regards >> >> Shashank >> >> >> On 2/6/2018 6:28 PM, Vidya Srinivas wrote: >>> From: Mahesh Kumar <mahesh1.kumar@intel.com> >>> >>> Add support of recognizing DRM_FORMAT_NV12 from plane_format >> register >>> value. >>> >>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> >>> --- >>> drivers/gpu/drm/i915/intel_display.c | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c >>> b/drivers/gpu/drm/i915/intel_display.c >>> index 60ba5bb..e3a6a7f 100644 >>> --- a/drivers/gpu/drm/i915/intel_display.c >>> +++ b/drivers/gpu/drm/i915/intel_display.c >>> @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool >> rgb_order, bool alpha) >>> switch (format) { >>> case PLANE_CTL_FORMAT_RGB_565: >>> return DRM_FORMAT_RGB565; >>> + case PLANE_CTL_FORMAT_NV12: >>> + return DRM_FORMAT_NV12; >> I dont think this is correct, the case PLANE_CTL_FORMAT_NV12 is defined as >> (1 << 24) but when I check bspec definition, 24th bit is set for >> P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are >> 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This means we >> have mixed NV12 format with P0xx formats. When I checked the definition >> of DRM_FORMAT_NV12, I am not sure if that's intended for this. Ville, I saw >> that the DRM_FORMAT_NV12 definition was added by you, can you please >> comment if this is the right usage ? >> > Upto Gen10 24-27 bits of PLANE_CTL will be used for format. ICL onwards 23rd bit > is also used. PLANE_CTL_FORMAT_MASK has been defined in i915_reg.h > and mapping will be same if 23rd bit is 0. For NV12, 1<< 24 thus holds good > for all Gen. That's not my point. What I want to say is, as per bspec (1 << 24) is for P010/P012/P016 formats, not NV12. NV12 is 8 bit YCBCR 4:2:0 format whereas P010/012/016 are 10,12 and 16 bit YCBCR 4:2:0 formats. So I was not sure if that should be called NV12 and hence I was not sure if we should return DRM_FORMAT_NV12 for the same. - Shashank >>> default: >>> case PLANE_CTL_FORMAT_XRGB_8888: >>> if (rgb_order) {
Regards Shashank On 2/8/2018 10:02 AM, Sharma, Shashank wrote: > > > On 2/8/2018 8:50 AM, Srinivas, Vidya wrote: >> >>> -----Original Message----- >>> From: Sharma, Shashank >>> Sent: Wednesday, February 7, 2018 9:22 PM >>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel- >>> gfx@lists.freedesktop.org >>> Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil >>> <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>; >>> Kumar, Mahesh1 <mahesh1.kumar@intel.com> >>> Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in >>> skl_format_to_fourcc >>> >>> Regards >>> >>> Shashank >>> >>> >>> On 2/6/2018 6:28 PM, Vidya Srinivas wrote: >>>> From: Mahesh Kumar <mahesh1.kumar@intel.com> >>>> >>>> Add support of recognizing DRM_FORMAT_NV12 from plane_format >>> register >>>> value. >>>> >>>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> >>>> --- >>>> drivers/gpu/drm/i915/intel_display.c | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/i915/intel_display.c >>>> b/drivers/gpu/drm/i915/intel_display.c >>>> index 60ba5bb..e3a6a7f 100644 >>>> --- a/drivers/gpu/drm/i915/intel_display.c >>>> +++ b/drivers/gpu/drm/i915/intel_display.c >>>> @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool >>> rgb_order, bool alpha) >>>> switch (format) { >>>> case PLANE_CTL_FORMAT_RGB_565: >>>> return DRM_FORMAT_RGB565; >>>> + case PLANE_CTL_FORMAT_NV12: >>>> + return DRM_FORMAT_NV12; >>> I dont think this is correct, the case PLANE_CTL_FORMAT_NV12 is >>> defined as >>> (1 << 24) but when I check bspec definition, 24th bit is set for >>> P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are >>> 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This >>> means we >>> have mixed NV12 format with P0xx formats. When I checked the definition >>> of DRM_FORMAT_NV12, I am not sure if that's intended for this. >>> Ville, I saw >>> that the DRM_FORMAT_NV12 definition was added by you, can you please >>> comment if this is the right usage ? >>> >> Upto Gen10 24-27 bits of PLANE_CTL will be used for format. ICL >> onwards 23rd bit >> is also used. PLANE_CTL_FORMAT_MASK has been defined in i915_reg.h >> and mapping will be same if 23rd bit is 0. For NV12, 1<< 24 thus >> holds good >> for all Gen. > That's not my point. What I want to say is, as per bspec (1 << 24) is > for P010/P012/P016 formats, not NV12. NV12 is 8 bit YCBCR 4:2:0 format > whereas P010/012/016 are 10,12 and 16 bit YCBCR 4:2:0 formats. So I > was not sure if that should be called NV12 and hence I was not sure if > we should return DRM_FORMAT_NV12 for the same. > - Shashank What I mean to say here is, the check (1 << 24) is not good enough for all NV12, as you have to use it as if (mask == YCBCR_420_FORMAT_NV12) not (mask & YCBCR_420_FORMAT_NV12). But if that's how its intended to be used for future addition of P010/012/016, then I guess you can bypass this comment, but please make sure you differentiate NV12 with those formats. - Shashank >>>> default: >>>> case PLANE_CTL_FORMAT_XRGB_8888: >>>> if (rgb_order) { >
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 60ba5bb..e3a6a7f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) switch (format) { case PLANE_CTL_FORMAT_RGB_565: return DRM_FORMAT_RGB565; + case PLANE_CTL_FORMAT_NV12: + return DRM_FORMAT_NV12; default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) {