From patchwork Tue Feb 6 13:02:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srinivas, Vidya" X-Patchwork-Id: 10203041 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A95B660247 for ; Tue, 6 Feb 2018 13:04:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F324205AD for ; Tue, 6 Feb 2018 13:04:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 83CE92896A; Tue, 6 Feb 2018 13:04:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 271D1205AD for ; Tue, 6 Feb 2018 13:04:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4FEA6E411; Tue, 6 Feb 2018 13:04:26 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 603496E411 for ; Tue, 6 Feb 2018 13:04:26 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Feb 2018 05:04:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,468,1511856000"; d="scan'208";a="201609494" Received: from vsrini4-ubuntu.iind.intel.com ([10.223.161.6]) by fmsmga005.fm.intel.com with ESMTP; 06 Feb 2018 05:04:13 -0800 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Feb 2018 18:32:28 +0530 Message-Id: <1517922157-26011-8-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517922157-26011-1-git-send-email-vidya.srinivas@intel.com> References: <1517922157-26011-1-git-send-email-vidya.srinivas@intel.com> Subject: [Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 07fc084..d9801bf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4531,6 +4531,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint16_t ddb_allocation, int level, const struct skl_wm_params *wp, + const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */) { const struct drm_plane_state *pstate = &intel_pstate->base; @@ -4598,6 +4599,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } else { res_blocks++; } + + /* + * Make sure result blocks for higher latency levels are atleast + * as high as level below. + * Assumption in DDB algorithm optimization for special cases. + * Also covers Display WA #1125 for RC. + */ + if (result_prev->plane_res_b > res_blocks) + res_blocks = result_prev->plane_res_b; } if (INTEL_GEN(dev_priv) >= 11) { @@ -4680,6 +4690,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, for (level = 0; level <= max_level; level++) { struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] : &wm->wm[level]; + struct skl_wm_level *result_prev; + + if (level) + result_prev = plane_num ? &wm->uv_wm[level - 1] : + &wm->wm[level - 1]; + else + result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0]; ret = skl_compute_plane_wm(dev_priv, cstate, @@ -4687,6 +4704,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, ddb_blocks, level, wm_params, + result_prev, result); if (ret) return ret;