Message ID | 1518584256-25253-17-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
My previous review comment for alignment has not been addressed in this series Regards Shashank On 2/14/2018 10:27 AM, Vidya Srinivas wrote: > If the fb format is YUV, enable the plane CSC mode bits > for the conversion. > > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 10edacc..baf197b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6453,6 +6453,12 @@ enum { > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ > #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) > #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) > +#define PLANE_COLOR_CSC_MASK (0x7 << 17) > +#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) > +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) > #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) > #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) > #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 42ec089..6c43eef 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, > plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; > plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; > plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); > + if (fb && intel_format_is_yuv(fb->format->format)) > + plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; > > return plane_color_ctl; > }
My previous review comment for alignment is not addressed in this patch. Regards Shashank On 2/14/2018 10:27 AM, Vidya Srinivas wrote: > If the fb format is YUV, enable the plane CSC mode bits > for the conversion. > > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 10edacc..baf197b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6453,6 +6453,12 @@ enum { > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ > #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) > #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) > +#define PLANE_COLOR_CSC_MASK (0x7 << 17) > +#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) > +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) > #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) > #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) > #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 42ec089..6c43eef 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, > plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; > plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; > plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); > + if (fb && intel_format_is_yuv(fb->format->format)) > + plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; > > return plane_color_ctl; > }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10edacc..baf197b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6453,6 +6453,12 @@ enum { #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) +#define PLANE_COLOR_CSC_MASK (0x7 << 17) +#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 42ec089..6c43eef 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); + if (fb && intel_format_is_yuv(fb->format->format)) + plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; return plane_color_ctl; }
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+)