From patchwork Wed Feb 14 14:13:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 10219101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6496660467 for ; Wed, 14 Feb 2018 14:20:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56499288FC for ; Wed, 14 Feb 2018 14:20:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4ADE628FEE; Wed, 14 Feb 2018 14:20:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D6FE4288FC for ; Wed, 14 Feb 2018 14:20:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D9FE6E404; Wed, 14 Feb 2018 14:20:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDB496E416 for ; Wed, 14 Feb 2018 14:20:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Feb 2018 06:20:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,512,1511856000"; d="scan'208";a="204076966" Received: from mint-dev.iind.intel.com ([10.223.25.164]) by fmsmga005.fm.intel.com with ESMTP; 14 Feb 2018 06:20:45 -0800 From: Ramalingam C To: seanpaul@chromium.org, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com, daniel.vetter@ffwll.ch Date: Wed, 14 Feb 2018 19:43:41 +0530 Message-Id: <1518617638-21684-27-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518617638-21684-1-git-send-email-ramalingam.c@intel.com> References: <1518617638-21684-1-git-send-email-ramalingam.c@intel.com> Subject: [Intel-gfx] [PATCH 26/43] drm/i915: Define Intel HDCP2.2 registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomas.winkler@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Intel HDCP2.2 registers are defined with addr offsets and bit details. Macros are defined for referencing the register offsets based on the port index. Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/i915_reg.h | 120 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f6afa5e5e7c1..6a57b12d8dab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2268,6 +2268,126 @@ enum i915_power_well_id { _PORT_TX_DW14_LN0_C) + \ _BXT_LANE_OFFSET(lane)) +/* + *HDCP Registers + **/ + +/* + * HW register offsets are incresing in the order of B, C, D, A, F, E. + * But enum value increses in the order of A, B, C, D, E, F. + * So port numbers are adjusted for offset calculations. + */ +#define HDCP_PORT_INDEX_ADJUST(p) (((p) == PORT_A ? PORT_E : \ + (p) == PORT_E ? (0x6) : \ + (p)) - 1) +#define _MMIO_HDCP_PORT(p, a, b) _MMIO_PORT(HDCP_PORT_INDEX_ADJUST(p), \ + a, b) + + +/* RO Registers for I915. Programmable from FW(ME) only */ +#define HDCP2_AUTH_DDI_A 0x66898 +#define HDCP2_AUTH_DDI_B 0x66598 +#define HDCP2_AUTH_DDI_C 0x66698 +#define HDCP2_AUTH_DDI_D 0x66798 +#define HDCP2_AUTH_DDI_E 0x66A98 +#define HDCP2_AUTH_DDI_F 0x66998 +#define AUTH_LINK_AUTHENTICATED (1 << 31) +#define AUTH_LINK_TYPE (1 << 30) +#define AUTH_FORCE_CLR_INPUTCTR (1 << 19) +#define AUTH_CLR_KEYS (1 << 18) + +#define HDCP2_AUTH_DDI(port) _MMIO_HDCP_PORT(port, \ + HDCP2_AUTH_DDI_B, \ + HDCP2_AUTH_DDI_C) + + +/* Multi stream DP registers */ +/* RO Registers for I915. Programmable from FW(ME) only */ +#define HDCP2_AUTH_STREAM_A 0x66F00 +#define HDCP2_AUTH_STREAM_B 0x66F04 +#define HDCP2_AUTH_STREAM_C 0x66F08 +#define HDCP2_AUTH_STREAM_D 0x66F0C +#define AUTH_STREAM_TYPE (1 << 31) + +#define HDCP2_AUTH_STREAM(stream) _MMIO_PORT(stream, \ + HDCP2_AUTH_STREAM_A, \ + HDCP2_AUTH_STREAM_B) + +/* RW Registers for I915 */ +#define HDCP2_CTL_DDI_A 0x668B0 +#define HDCP2_CTL_DDI_B 0x665B0 +#define HDCP2_CTL_DDI_C 0x666B0 +#define HDCP2_CTL_DDI_D 0x667B0 +#define HDCP2_CTL_DDI_E 0x66AB0 +#define HDCP2_CTL_DDI_F 0x669B0 +#define CTL_LINK_ENCRYPTION_REQ (1 << 31) +#define CTL_VBID_TYPE_SELECT_SHIFT 29 +#define CTL_VBID_TYPE_SELECT_MASK (3 << CTL_VBID_TYPE_SELECT_SHIFT) + +#define HDCP2_CTR_DDI(port) _MMIO_HDCP_PORT(port, HDCP2_CTL_DDI_B, \ + HDCP2_CTL_DDI_C) + +/* RO only. For Debug purpose */ +#define HDCP2_INPUTCTR_DDI_A 0x668B8 +#define HDCP2_INPUTCTR_DDI_B 0x665B8 +#define HDCP2_INPUTCTR_DDI_C 0x666B8 +#define HDCP2_INPUTCTR_DDI_D 0x667B8 +#define HDCP2_INPUTCTR_DDI_E 0x66AB8 +#define HDCP2_INPUTCTR_DDI_F 0x669B8 + +#define HDCP2_INPUTCTR_LO_DDI(port) _MMIO_HDCP_PORT(port, \ + HDCP2_INPUTCTL_DDI_B, \ + HDCP2_INPUTCTL_DDI_C) + +#define HDCP2_INPUTCTR_HI_DDI(port) _MMIO_HDCP_PORT(port, \ + (HDCP2_INPUTCTL_DDI_B + 4), \ + (HDCP2_INPUTCTL_DDI_C + 4)) + +/* RO Registers for I915. Programmable from FW(ME) only */ +#define HDCP2_RIV_DDI_A 0x66890 +#define HDCP2_RIV_DDI_B 0x66590 +#define HDCP2_RIV_DDI_C 0x66690 +#define HDCP2_RIV_DDI_D 0x66790 +#define HDCP2_RIV_DDI_E 0x66A90 +#define HDCP2_RIV_DDI_F 0x66990 + +#define HDCP2_RIV_LO_DDI(port) _MMIO_HDCP_PORT(port, HDCP2_RIV_DDI_B, \ + HDCP2_RIV_DDI_C) + +#define HDCP2_RIV_HI_DDI(port) _MMIO_HDCP_PORT(port, \ + (HDCP2_RIV_DDI_B + 4), \ + (HDCP2_RIV_DDI_C + 4)) + +/* RO only. For Debug purpose */ +#define HDCP2_STATUS_DDI_A 0x668B4 +#define HDCP2_STATUS_DDI_B 0x665B4 +#define HDCP2_STATUS_DDI_C 0x666B4 +#define HDCP2_STATUS_DDI_D 0x667B4 +#define HDCP2_STATUS_DDI_E 0x66AB4 +#define HDCP2_STATUS_DDI_F 0x669B4 +#define STREAM_ENCRYPTION_STATUS_A (1 << 31) +#define STREAM_ENCRYPTION_STATUS_B (1 << 30) +#define STREAM_ENCRYPTION_STATUS_C (1 << 29) +#define LINK_TYPE_STATUS (1 << 22) +#define LINK_AUTH_STATUS (1 << 21) +#define LINK_ENCRYPTION_STATUS (1 << 20) + +#define HDCP2_STATUS_DDI(port) _MMIO_HDCP_PORT(port, \ + HDCP2_STATUS_DDI_B, \ + HDCP2_STATUS_DDI_C) + +/* RO only. For Debug purpose */ +#define HDCP2_STREAM_STATUS_A 0x668C0 +#define HDCP2_STREAM_STATUS_B 0x665C0 +#define HDCP2_STREAM_STATUS_C 0x666C0 +#define HDCP2_STREAM_STATUS_D 0x667C0 +#define STREAM_ENCRYPTION_STATUS (1 << 31) +#define STREAM_TYPE_STATUS (1 << 30) + +#define HDCP2_STREAM_STATUS(stream) _MMIO_HDCP_PORT(stream, \ + HDCP2_STREAM_STATUS_B, \ + HDCP2_STREAM_STATUS_C) + /* UAIMI scratch pad register 1 */ #define UAIMI_SPR1 _MMIO(0x4F074) /* SKL VccIO mask */