From patchwork Wed Feb 14 14:13:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 10219049 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 78D6A602CB for ; Wed, 14 Feb 2018 14:19:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 698EA288FC for ; Wed, 14 Feb 2018 14:19:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E0BF28FEF; Wed, 14 Feb 2018 14:19:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F3DCD28FEE for ; Wed, 14 Feb 2018 14:19:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C54389E59; Wed, 14 Feb 2018 14:19:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A35CE89DA3 for ; Wed, 14 Feb 2018 14:19:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Feb 2018 06:19:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,512,1511856000"; d="scan'208";a="204076668" Received: from mint-dev.iind.intel.com ([10.223.25.164]) by fmsmga005.fm.intel.com with ESMTP; 14 Feb 2018 06:19:49 -0800 From: Ramalingam C To: seanpaul@chromium.org, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com, daniel.vetter@ffwll.ch Date: Wed, 14 Feb 2018 19:43:17 +0530 Message-Id: <1518617638-21684-3-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518617638-21684-1-git-send-email-ramalingam.c@intel.com> References: <1518617638-21684-1-git-send-email-ramalingam.c@intel.com> Subject: [Intel-gfx] [PATCH 02/43] drm: HDMI and DP specific HDCP2.2 defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomas.winkler@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In preparation for implementing HDCP2.2 in I915, this patch adds HDCP register definitions for HDMI and DP HDCP adaptations. HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where are HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h. Signed-off-by: Ramalingam C --- include/drm/drm_dp_helper.h | 59 +++++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_hdcp.h | 37 ++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c239e6e24a10..28a4dfbc2613 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -857,6 +857,65 @@ #define DP_AUX_HDCP_KSV_FIFO 0x6802C #define DP_AUX_HDCP_AINFO 0x6803B +/** + * DP HDCP2.2 parameter offsets in DPCD address space + */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/** + * DP HDCP message start offsets in DPCD address space + */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +union hdcp2_dp_rx_status { + struct { + uint8_t ready:1; + uint8_t hprime_available:1; + uint8_t paring_available:1; + uint8_t reauth_req:1; + uint8_t Link_integrity_failure:1; + uint8_t rsvd:3; + } fields; + uint8_t val; +} __packed; + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE 0x0 diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index 9661c700cebb..c5f36b1a004b 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -264,4 +264,41 @@ struct hdcp2_dp_errata_stream_type { uint8_t stream_type; } __packed; +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200 +#define HDCP_2_2_PAIRING_TIMEOUT 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT 20 +#define HDCP_2_2_DP_LPRIME_TIMEOUT 7 +#define HDCP_2_2_RECVID_LIST_TIMEOUT 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT 100 + +/* HDMI HDCP2.2 Register Offsets */ +#define HDMI_HDCP_2_2_REG_VER_OFFSET 0x50 +#define HDMI_HDCP_2_2_REG_WR_MSG_OFFSET 0x60 +#define HDMI_HDCP_2_2_REG_RXSTATUS_OFFSET 0x70 +#define HDMI_HDCP_2_2_REG_RD_MSG_OFFSET 0x80 +#define HDMI_HDCP_2_2_REG_DBG_OFFSET 0xC0 + +#define HDMI_HDCP_2_2_SUPPORT_MASK (1<<2) +#define HDCP_RXCAPS_VERSION_HDCP_2_2_VAL 0x2 + +#define DRM_HDCP_MAX_AUX_LEN 16 + +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 + +union hdcp2_hdmi_rx_status { + struct { + uint8_t msg_sz_hi:2; + uint8_t ready:1; + uint8_t reauth_req:1; + uint8_t reserved:4; + uint8_t msg_sz_lo; + } fields; + uint16_t val; +} __packed; + #endif