| Message ID | 1519208444-16665-11-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Regards Shashank On 2/21/2018 3:50 PM, Vidya Srinivas wrote: > From: Chandra Konduru <chandra.konduru@intel.com> > > This patch sets appropriate scaler mode for NV12 format. > In this mode, skylake scaler does either chroma-upsampling or > chroma-upsampling and resolution scaling > > v2: Review comments from Ville addressed > NV12 case to be checked first for setting > the scaler > > v3: Rebased (me) > > v4: Rebased (me) > > v5: Missed the Tested-by/Reviewed-by in the previous series > Adding the same to commit message in this version. > > v6: Rebased (me) > > v7: Rebased (me) > > v8: Rebased (me) > Restricting the NV12 change for scaler to BXT and KBL > in this series. > > v9: Rebased (me) > > v10: As of now, NV12 has been tested on Gen9 and Gen10. However, > code is applicable to all GEN >= 9. Hence making > that change to keep it generic. > Comments under v8 is not valid anymore. > > v11: Addressed review comments by Shashank Sharma. > For Gen10+, the scaler mode to be set it planar or normal > (single bit). Changed the code to be applicable to all > Gen. > > v12: Addressed review comments from Shashank Sharma > For Gen9 (apart from GLK) bits 28:29 to be programmed > in PS_CTRL for NV12. For GLK and Gen10+, bit 29 to be set > for all Planar. > > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_atomic.c | 13 +++++++++++-- > 2 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1412abc..4349d81 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6732,6 +6732,8 @@ enum { > #define PS_SCALER_MODE_MASK (3 << 28) > #define PS_SCALER_MODE_DYN (0 << 28) > #define PS_SCALER_MODE_HQ (1 << 28) > +#define SKL_PS_SCALER_MODE_NV12 (2 << 28) > +#define PS_SCALER_MODE_PLANAR (1 << 29) > #define PS_PLANE_SEL_MASK (7 << 25) > #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) > #define PS_FILTER_MASK (3 << 23) > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c > index e9fb6920..5b2ae8c 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -328,8 +328,17 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, > } > > /* set scaler mode */ > - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { > - scaler_state->scalers[*scaler_id].mode = 0; > + if ((INTEL_GEN(dev_priv) >= 9) && > + plane_state && plane_state->base.fb && > + plane_state->base.fb->format->format == > + DRM_FORMAT_NV12) { > + if (INTEL_GEN(dev_priv) == 9 && > + !IS_GEMINILAKE(dev_priv)) > + scaler_state->scalers[*scaler_id].mode = > + SKL_PS_SCALER_MODE_NV12; > + else > + scaler_state->scalers[*scaler_id].mode = > + PS_SCALER_MODE_PLANAR; > } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { > /* > * when only 1 scaler is in use on either pipe A or B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1412abc..4349d81 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6732,6 +6732,8 @@ enum { #define PS_SCALER_MODE_MASK (3 << 28) #define PS_SCALER_MODE_DYN (0 << 28) #define PS_SCALER_MODE_HQ (1 << 28) +#define SKL_PS_SCALER_MODE_NV12 (2 << 28) +#define PS_SCALER_MODE_PLANAR (1 << 29) #define PS_PLANE_SEL_MASK (7 << 25) #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) #define PS_FILTER_MASK (3 << 23) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index e9fb6920..5b2ae8c 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -328,8 +328,17 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, } /* set scaler mode */ - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { - scaler_state->scalers[*scaler_id].mode = 0; + if ((INTEL_GEN(dev_priv) >= 9) && + plane_state && plane_state->base.fb && + plane_state->base.fb->format->format == + DRM_FORMAT_NV12) { + if (INTEL_GEN(dev_priv) == 9 && + !IS_GEMINILAKE(dev_priv)) + scaler_state->scalers[*scaler_id].mode = + SKL_PS_SCALER_MODE_NV12; + else + scaler_state->scalers[*scaler_id].mode = + PS_SCALER_MODE_PLANAR; } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { /* * when only 1 scaler is in use on either pipe A or B,