From patchwork Fri Feb 23 15:55:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav K Singh X-Patchwork-Id: 10238191 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3B822602DC for ; Fri, 23 Feb 2018 15:56:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A9CC2975A for ; Fri, 23 Feb 2018 15:56:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E5C82975F; Fri, 23 Feb 2018 15:56:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5FEC82975A for ; Fri, 23 Feb 2018 15:56:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4B8B6F1D4; Fri, 23 Feb 2018 15:56:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA6FF6F1D4 for ; Fri, 23 Feb 2018 15:56:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Feb 2018 07:56:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,383,1515484800"; d="scan'208";a="32284168" Received: from gksingh.iind.intel.com ([10.66.247.92]) by fmsmga004.fm.intel.com with ESMTP; 23 Feb 2018 07:56:36 -0800 From: Gaurav K Singh To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Feb 2018 21:25:44 +0530 Message-Id: <1519401353-25029-2-git-send-email-gaurav.k.singh@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401353-25029-1-git-send-email-gaurav.k.singh@intel.com> References: <1519401353-25029-1-git-send-email-gaurav.k.singh@intel.com> Subject: [Intel-gfx] [PATCH 01/10] drm: i915: Defining Compression Capabilities X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For Vesa Display Stream compression, defining structures for compression capabilities to be stored in encoder. Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/i915_drv.h | 125 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 62 +++++++++++++++++++ include/drm/drm_dp_helper.h | 1 + 3 files changed, 188 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0d8cb74e7d02..4b1c323c0925 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -780,6 +780,131 @@ struct i915_psr { void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *); }; +/* DSC Configuration structure */ +#define NUM_BUF_RANGES 15 + +/* Configuration for a single Rate Control model range */ +struct rc_range_parameters { + /* Min Quantization Parameters allowed for this range */ + unsigned long range_min_qp; + /* Max Quantization Parameters allowed for this range */ + unsigned long range_max_qp; + /* Bits/group offset to apply to target for this group */ + unsigned long range_bpg_offset; +}; + +struct vdsc_config { + /* Bits / component for previous reconstructed line buffer */ + unsigned long line_buf_depth; + /* + * Rate control buffer size (in bits); not in PPS, + * used only in C model for checking overflow + */ + unsigned long rc_bits; + /* Bits per component to code (must be 8, 10, or 12) */ + unsigned long bits_per_component; + /* + * Flag indicating to do RGB - YCoCg conversion + * and back (should be 1 for RGB input) + */ + bool convert_rgb; + unsigned long slice_count; + /* Slice Width */ + unsigned long slice_width; + /* Slice Height */ + unsigned long slice_height; + /* + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens + * outside of DSC encode/decode algorithm) + */ + bool enable422; + /* Picture Width */ + unsigned long pic_width; + /* Picture Height */ + unsigned long pic_height; + /* Offset to bits/group used by RC to determine QP adjustment */ + unsigned long rc_tgt_offset_high; + /* Offset to bits/group used by RC to determine QP adjustment */ + unsigned long rc_tgt_offset_low; + /* Bits/pixel target << 4 (ie., 4 fractional bits) */ + unsigned long bits_per_pixel; + /* + * Factor to determine if an edge is present based + * on the bits produced + */ + unsigned long rc_edge_factor; + /* Slow down incrementing once the range reaches this value */ + unsigned long rc_quant_incr_limit1; + /* Slow down incrementing once the range reaches this value */ + unsigned long rc_quant_incr_limit0; + /* Number of pixels to delay the initial transmission */ + unsigned long initial_xmit_delay; + /* Number of pixels to delay the VLD on the decoder,not including SSM */ + unsigned long initial_dec_delay; + /* Block prediction range (in pixels) */ + bool block_pred_enable; + /* Bits/group offset to use for first line of the slice */ + unsigned long first_line_bpg_Ofs; + /* Value to use for RC model offset at slice start */ + unsigned long initial_offset; + /* X position in the picture of top-left corner of slice */ + unsigned long x_start; + /* Y position in the picture of top-left corner of slice */ + unsigned long y_start; + /* Thresholds defining each of the buffer ranges */ + unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1]; + /* Parameters for each of the RC ranges */ + struct rc_range_parameters rc_range_params[NUM_BUF_RANGES]; + /* Total size of RC model */ + unsigned long rc_model_size; + /* Minimum QP where flatness information is sent */ + unsigned long flatness_minQp; + /* Maximum QP where flatness information is sent */ + unsigned long flatness_maxQp; + /* + * MAX-MIN for all components is required to + * be <= this value for flatness to be used + */ + unsigned long flatness_det_thresh; + /* Initial value for scale factor */ + unsigned long initial_scale_value; + /* Decrement scale factor every scale_decrement_interval groups */ + unsigned long scale_decrement_interval; + /* Increment scale factor every scale_increment_interval groups */ + unsigned long scale_increment_interval; + /* Non-first line BPG offset to use */ + unsigned long nfl_bpg_offset; + /* BPG offset used to enforce slice bit */ + unsigned long slice_bpg_offset; + /* Final RC linear transformation offset value */ + unsigned long final_offset; + /* Enable on-off VBR (ie., disable stuffing bits) */ + bool vbr_enable; + /* Mux word size (in bits) for SSM mode */ + unsigned long mux_word_size; + /* + * The (max) size in bytes of the "chunks" that are + * used in slice multiplexing + */ + unsigned long chunk_size; + /* Placeholder for PPS identifier */ + unsigned long pps_identifier; + /* DSC Minor Version */ + unsigned long dsc_version_minor; + /* DSC Major version */ + unsigned long dsc_version_major; + /* Number of VDSC engines */ + unsigned long num_vdsc_instances; +}; + +/* Compression caps stored in encoder */ +struct i915_compression_params { + bool compression_support; + unsigned long compression_bpp; + struct vdsc_config dsc_cfg; + unsigned char slice_count; +}; + enum intel_pch { PCH_NONE = 0, /* No PCH present */ PCH_IBX, /* Ibexpeak PCH */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5853d92a6512..6e1b907990bf 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -954,6 +954,63 @@ struct intel_dp_compliance { u8 test_lane_count; }; +/* Vesa Display Stream Capability of DP Sink */ +struct dp_sink_dsc_caps { + /* Display Stream Compression Support */ + bool is_dsc_supported; + u8 dsc_major_ver; + u8 dsc_minor_ver; + u16 rcbuffer_blocksize; + /* n+1 value */ + u16 rcbuffer_size_in_blocks; + unsigned long rcbuffer_size; + + union { + u8 slice_caps; + struct { + u8 one_slice_per_line_support : 1; + u8 two_slice_per_line_support : 1; + u8 slice_caps_reserved1 : 1; + u8 four_slice_per_line_support : 1; + u8 slice_caps_reserved2 : 4; + }; + }; + /* Decode line buffer bits of precision */ + unsigned long line_buffer_bit_depth; + bool is_block_pred_supported; + unsigned long sink_support_max_bpp; + + union { + u8 color_format_caps; + struct { + u8 RGB_support : 1; + u8 YCbCr444_support : 1; + u8 YCbCr422_support : 1; + u8 color_format_caps_reserved : 5; + }; + }; + + union { + u8 color_depth_caps; + struct { + u8 color_depth_caps_reserved1 : 1; + u8 support_8bpc : 1; + u8 support_10bpc : 1; + u8 support_12bpc : 1; + u8 color_depth_caps_reserved2 : 4; + }; + }; + + u16 slice_height; + u16 slice_width; + /* Y Resolution */ + u16 pic_height; + /* X Resolution */ + u16 pic_width; +}; + + + struct intel_dp { i915_reg_t output_reg; i915_reg_t aux_ch_ctl_reg; @@ -971,6 +1028,8 @@ struct intel_dp { uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; + uint8_t dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; + uint8_t fec_dpcd; /* source rates */ int num_source_rates; const int *source_rates; @@ -1046,6 +1105,9 @@ struct intel_dp { /* Displayport compliance testing */ struct intel_dp_compliance compliance; + + /* For Vesa Display Stream Compression Support */ + struct i915_compression_params compr_params; }; struct intel_lspcon { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index da58a428c8d7..05f811c50d28 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -896,6 +896,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 +#define DP_DSC_RECEIVER_CAP_SIZE 0xb void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);